SU1474716A1 - Data compression unit - Google Patents

Abstract

The invention relates to digital computing and the transfer of measurement information and is intended to compress data (for example, data from analog-to-digital conversion of signals) by piecewise-linear approximation of the original functional relationship that this data represents. The purpose of the invention is to increase the information content of the device. The device contains adders 1,8,9,10, counter 2, control block 3, registers 4,5, multiplier 6, comparison block 7, subtractor 11, code converter 12. The device carries out approximation by straight line segments, which is obtained as a result of connecting by straight line adjacent points (YI, TI) (I = 0,1,2,3, ...). (YI is the value of the I-th reference

TI - the corresponding value of the argument TI = ΣΔtI

ΔTI = TI + 1-TI = 1). The approximation is realized by the criterion of uniform approximation with an error δ. The adder 10 calculates a feature value FI according to the expression FI-FI = 1 + ΔFI, where Δ _I = ΔY ^_I. T _I-1 -Y _I-1 , ΔY _I = Y _I- Y _{I -1} , Y _I-1 = Y _I-1 -Y ₀ . A higher compression factor is provided by the implementation of the following criterion of sampling of significant samples: the next significant sample is selected if the inequality / FI / ≤δ ^{* is} violated upon receipt of the first sample ^. TI, where δ ^* = δ / 3. The device has a high noise immunity, since the processing is based on the integration operation. 1 hp f-ly. 4 il.

Description

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ABOUT

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6, block 7 comparison, subtractor 11, code converter 12. The device carries out approximation by straight line segments, which is obtained as a result of connecting by straight line adjacent points (Y ;, t;) (i 0,1,2,3, ...) (Y; i-ro value t; is the corresponding argument value

t; &t; t, 4l - t; one).

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Approximation is realized according to the criterion of uniform approximation with an error of $. In the adder 10, the value of the function F1 is calculated in accordance with the expression F; F, + &F; where UF; DU, t, Vl- y, where, in turn, and y; Y; - Y, -.,, U.,

 Y -m - Y0. A higher compression factor is provided by implementing the following criterion of sampling of significant samples: the next substantial sample is chosen if the inequality is violated upon receipt of the 1st sample. t; where}) f / 3. The device has high noise immunity, as the processing is based on the integration operation. 1 h, para. f-ly, 4 ill.

one

The invention relates to digital computing and the transfer of measurement information and is intended to compress data, such as data from an analog-digital signal conversion, by piecewise linear approximation of the original functional relationship that this data represents.

The purpose of the invention is to increase the information content of the device.

FIG. 1 shows a functional diagram of a device for compressing information; on fkg. 2 is a diagram of the operation of the control unit; Fig. 3 is a functional block diagram of the control unit; in fig. 4 - graphical interpretation of the essence of the calculations performed in the device.

The proposed device contains (FIG. 1) adder 1, counter 2, control block 3, first register 4, second register 5, multiplier 6, comparison block 7, second adder 8, third adder 9, fourth adder 10, subtractor 11, converter 12 code.

The control unit 3 has the first 13, second 14, third 15 and fourth 1 6 outputs, the first - the fourth 17-20 inputs.

The device also contains a bus 21 logical 1.

The control unit 3 contains (FIG. 3) AND-HE elements 22 and 23, the AND 24 element, the register 25, the decoder 26, the OR elements 27 and 28 and the inverter 29.

The device compresses the data by approximation by segments

straight polyline, which is obtained by connecting straight segments of adjacent points Y ;, t; s (i 0,1,2,3, ...), Y; - this value

1st count, tj - the corresponding value of the argument. Sequences of values Y ;, t; are data that is compressed. T0 0 is assumed as well

that t; 2lKt-, where u t; t 41 -t; one . Ui

The approximation is carried out according to the criterion of uniform approximation with a 5 error of $. The error is provided when the S / 3 device is set to 8 S / 3.

To implement the specified approximation, the device calculates the value of the function FJ in accordance with the expression

F; F ;, + & F, (1),

where DG; “Uy; t-, - y;.,, (2)

five

where in turn

Remote control; ; - Y,. (,

(3) (4)

v y - Y

U, -1 1-1L0

0 The values of (F;) coincide with the values of the difference uS (t;) in the known device.

Upon receipt of each 1st count Y; the value of the function F is calculated; and checks for inequality

/ F; / ЈD ,, (5)

where DJ Z1S At; t ;.

(63

If inequality (5) at the i-th step is not violated, then the approximated broken line represented by i links can be approximated with an error O with a straight line segment, bounded on one side by Y0, t0, and ac by the Y point; , t; . The processing in this case is not interrupted by

If inequality (5) at the i-th step is violated, then the broken line may not be approximated with an error of the indicated straight line segment. In this case, the approximation process is interrupted and the device approximates a polyline represented by (1-1) units, a straight line bounded by the points Y0, t0 and Y ,,, t, - (. Ґ and the corresponding value of the argument tN t ;,. In the next approximation interval, the value of Y will be Y, a y,, - y

1 1-11 OSummer 8 (combination) performs the formation of a difference (4).

In counter 2, the value of the argument t;,.

The control unit 3 controls the processes of receiving data from the source of computations and issuing compressed data to the consumer. The operation of the control unit is described (Fig. 2) by a flowchart that uniquely identifies the input and output sequences of control signals.

The first register 4 is intended to store the values of the previous reference Y, -M.

The second register 5 is designed to store the value of Y0 (or the value of the previous substantial reference).

The multiplier 6 forms the value of the product Dy; - t, 1-., To calculate the expression (2).

Comparison unit 7 checks the fulfillment of inequality (5).

The first adder 1 (Raman performs the formation of the difference (3).

In the third (accumulating) adder 9, the values of DJ are calculated in accordance with (6).

The fourth (accumulating) adder 1 0 implements the calculation of the values of F- in accordance with the expression ()

In the subtractor I, the values of the others are calculated (in accordance with the expression (2).

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Converter 1 2 code is designed to form the absolute function of the function F; . As it can be used direct number to additional number converter.

The device works as follows.

Before the start of work, the master course $ / 3 of the device is set to the required value 5, the initial zero value is set at the input Y of the current sample receiving Yt, the control unit 3 is set to the initial state, the first register 4 As a result, the values of Y0, Y; M, t, take initial zero values, and the control bpoc 3 falls into the A1 state (Fig. 2)

one . In state A, the control unit 3 generates a command at output 14. At the same time, the read signal from the output device reads a significant count YN and the corresponding argument value tN from the outputs YN and tw devices are read by the consumer.

2. Then block 3 of control (in state A2) issues a command from output 16, which leads to the detection of adder 9 (D; 0). adder 10

(F, 0) and counter 2.

3. Further, the control unit 3 (in the state A3) performs the issuance of the command from output 13. By which the following occurs:

in the first register 4 record with input Y; the device has the value of a hectare count of Y ,, which then becomes the previous count of Y, t;

unit 2 is added to counter 2, and thus, the value of

WITH -

from the output. The request of the device is sent to the data source, an upstream signal is sent to the data source, which causes the logical O. levels to form a source on the input 17 of the device.

4. After that, the control unit 3 switches to the A-4 state of waiting for the next sample from the data source. The data source at input Y, the device sets the value of the next reference (in the additional code) and notifies the compression device by setting the input level at & t4 to logical 1.

5. Having detected the logical 1 at input 17, the control unit 3 issues in state A5 from output 15 to the control inputs of adders 9 and 1 O, which in the adder 10 forms the new value of function F; in accordance with the expression (1), and in the adder 9 - the new value of D in accordance with the expression (6).

The value of the FG is formed at the information input of the fourth adder 10. The formation starts from the moment of input to input Y; the device of the current counting value Y ". The difference (3) is calculated by the first adder 1 as follows: the second input of the adder 1 receives the value YJ from the input Y; device, the first input is the inverted code of the number Y ;, from the inverting output of the first register 4, and the transfer input is logical 1, the calculation of the difference (4) by the second adder 8 is performed as follows: the second input of the adder 8 receives the direct code of the number Y} - from the direct output of the first register 4, to the first - the inverted code of the number YQ from the output of the second register 5, and to the transfer input - logical 1. The multiplier 6 calculates the product uy; t, e where the first factor goes to the multiplier from the output of the adder 8, and the second goes from the output of the counter 2. The value of this product goes to the first input of the subtractor 11, the value of st, to the second input of the subtractor 1 1 and thus its output forms the value of DR. .

A command from the output 15 of the control unit 3 is issued after the UF value is cut; will be formed (the condition is feasible by selecting the clock frequency in the control unit).

6 o After the values of F and D are formed at the outputs of the adders 9 and 10, the comparison block 7 checks the fulfillment of the condition (5) If the condition is satisfied, then logical O is generated at the output of the circuit, otherwise the logical 1 The control unit 3 analyzes the signal arriving at its input 18 from the output of the comparison unit 7, and, depending on its value, decides on

6

The volume should be interrupted or continued processing at this interval of approximation: if logical 1 is detected, then the operation will continue, starting from point 1, if logical O is detected, then the operation will continue, starting from paragraph 3.

Claims (2)

1. A device for compressing information containing the first register, the first output of which is connected to the 5th first input of the first adder, the output of which is connected to the first input of the multiplier, the second register, the output of which is connected to the first input of the second adder, the third 0 adder, the output of which is connected to the first input of the comparison unit, and a counter, characterized in that, in order to increase the information content of the device, a fourth adder, a subtractor, a code converter, a logic unit bus and a control unit, the first input orogo is a control input of the device, the first control unit vy0 turn connected to first inputs of the first register and the counter and is input request unit, the second control unit output is connected to a first input of the second 35 register and is the output of the reading device, the third and fourth outputs of the control unit are connected respectively to the first inputs of the third and fourth adders and The 40 second inputs of the counter and the third and fourth adders, the second inputs of the first register and the first adder are combined and are the first information input of the device, 45 the second output of the first register is connected to the second inputs of the second register and the second adder and is an information output of the device, the output of the counter is the second information output of the device and is connected to the second input of the multiplier, the output of which is connected to the first input of the subtractor, the second input of which is connected to the output of the second 55 of the adder, the output of the subtractor is connected to the third input of the fourth adder, the output of which is connected to the second input of the comparator through a code converter, the output of which connected to the second input of the control unit 4, the third inputs of the first and second adders are connected to the bus of the logical unit, the third input of the third adder is the master input of the device, the third and fourth inputs of the control unit are respectively the clock input and the input of the initial installation of the device. 2. The device according to claim 1, characterized in that the control unit is configured on a register, a decoder, elements OR, AND, AND-NOT and an inverter, the output of which is connected to the first input of the element AND, the outputs of the first and second elements OR are connected to the first inputs of the same name NAND, whose outputs and output of the element I are connected respectively to the first, second and third inputs of the register, the outputs of which are connected to the corresponding information inputs of the decoder with Issuing a command from Exit U command output from exit 16 Command issued from exit 13 WITH The outputs of the zero and first bits of which are connected respectively with the second inputs of the first and second AND-NOT elements and the third input of the second AND-NOT elements and are respectively the second and first outputs of the unit, the first inputs of the second element OR and the input of the inverter, the outputs of the third and fourth bits of the decoder are connected respectively to the third input of the first AND-NO element and the first input of the first OR element and are respectively the fourth and third outputs of the unit, volts The second inputs of the second OR element and the AND element and the second input of the first OR element are the first and second inputs of the block, respectively; the sync inputs of the register and the decoder and the register setup input are the third and fourth inputs of the block, respectively. Start ; A1 A2 A3  The end FSh.2 } 27 22 28 23 2b 24 nineteen 20 Clock frequency Initial setup 26 About 1 2 3 Ј 11 15 them sixteen Fi.Z