SU1462477A1 - A-d converter - Google Patents

Abstract

The invention relates to aBTOMa-i tick and computing, namely, information for data converters, and can be used to convert analog values into a serial Galois field code, as well as in converters. codes. B a device containing an input bus 1, a group of comparators 2,; voltage divider 3, reference voltage bus 4, a group of elements EXCLUSIVE OR 5 in order to increase technological reliability due to the homogeneity of the structure a ring shift register 6 is entered, control inputs 7.8, a group of 9 NAND elements, bus 10 code half a Galois, exit tire II, 1 silt, 1 tab. (L S rnv

Description

I The invention relates to automation and computing, namely to information form converters and can be used to develop information in the device 1) converting analog values into i Galois field serial code, as well as in code converters.

The purpose of the invention is to increase the technical reliability due to the single representative input voltage measured.

The table shows an example of

at N 16, p 4 dp Uy 7 and 12.

affinity structure.

The drawing shows structures1.

,. scheme of the proposed analog-to-digital converter (ADC). ; The ADC contains an input bus 1, a group of 2 comparators, a divider 3 for example, a bus 4 for the reference voltage, a group of elements EXCLUSIVE OR 5, (a shift ring register 6, the first AGND device 7 input, | a control device 8 for the device, Irpynny elements AND-NOT 9, bus 10 Galois floor code, output bus I. Device. Works as follows

in a way.

Convertible input voltage. through the input bus 1 is applied to the first inputs of all comparators 2, the second inputs of which are supplied to the reference voltages taken from: the corresponding outputs of the divider 3, as a result of comparing the input: and the reference voltages at the outputs of the comparators 2 in the following mode is formed the unitary-parallel code i of the input value, which is fed to the inputs of the EXCLUSIVE OR 5 elements, at the outputs of the latter, a unit-position code of the input quantity is formed, which is fed to the information inputs of the ring register 6 shift.

For reading and remote transmission of information to the control bus 7 of the register of the shift register 6, a signal is given, which results in one of the memory elements of the register 6 writing a positional unit, a code formed at the outputs, a group of EXCLUSIVE OR 5. When fed to the second control A bus 8 connected to the register shift bus 6, a pack of p pulses is sequentially applied to the first inputs of the corresponding logical elements of the AND-NOT groups 9. At the same time, on the output bus 11 Twa will be generated code Galois, uniquely

Thus, the execution of the logs

10 of the proposed device in the form of a regular structure, containing in each channel the appropriately connected logical element EXCLUSIVE OR, a memory element

15 gistra shift and logical elements AND-NOT, ensures the uniformity of the structure of the device and increased reliability, which simplifies its microcircuit design.

20 The speed and complexity of the device is independent of the number of quantization levels of the input mode. Implemented in the proposed device new principle of transformation

 Information can be effectively applied to construct a wide class of transducers with remote transmission of readings in a discrete form.

thirty

Formula of found

Analog-to-digital converter content voltage divider, g

35 PU of p, where p is the number of levels of voltage forcing, of the elements of the SUIT CHAITSEEE OR, the group of n comparato, the first inputs of which are combined are the external bus, and the second

40 inputs are connected to the corresponding outputs of a voltage divider whose input is a reference reference voltage, the outputs of the comparators are connected to the first inputs of the corresponding

45 elements of the BASIC OR, and, the chrome of the first, with the second inputs of the previous elements of the EXCLUSIVE OR, the second input of the last element EXCLUSIVE OR is the zero sweat bus

yy), which differs from those that, in order to improve the technological reliability due to the homogeneous structure, an n-bit ring-shaped shift register and a group of AND-NOT elements are entered into it, the outputs of which are combined and are the output bus, the first inputs connected to the moves of the corresponding bits to the target shift register, and the second

developing information in the device

but represented input measured voltage.

The table shows an example of converting information into devices.

at N 16, p 4 dp Uy 7 and 12.

Thus, the implementation of the logical part of the device in the form of a regular structure containing in each channel the appropriately connected logical element EXCLUDING OR OR, the memory register of the shift register and the logical NAND element, ensures the uniformity of the device structure and increased reliability simplifies its microcircuit execution.

The speed and complexity of the implementation of the device does not depend on the number of quantization levels of the input quantity. The new principle of information transformation implemented in the proposed device can be effectively applied to construct a wide class of transducers with remote transmission of readings in a discrete form.

Formula of gain

An analog-to-digital converter, a content voltage divider, a group of n, where n is the number of voltage quantization levels, elements of FAILED ORE, a group of n comparators, the first inputs of which are combined and are the second bus, and the second

the inputs are connected to the corresponding outputs of a voltage divider, the input of which is the reference voltage, the outputs of the comparators are connected to the first inputs of the corresponding

ELEVATOR OR elements and, besides the first one, with the second inputs of the previous elements EXCLUSIVE OR, the second input of the last element EXCLUSIVE OR is a zero potential bus, characterized in that, in order to increase technological reliability due to the homogeneity of the structure, n-razra a circular ring shift register and a group of n I-NOT elements whose outputs are combined and are an output bus; the first inputs are connected to the outputs of the corresponding bits of the ring shift register, and the second

the inputs are the corresponding Galois field code buses, the information inputs of the ring shift register are connected to the outputs of the corresponding

the elements are EXCLUSIVE OR groups, and the first and second control inputs are read and read buses, respectively.

Claims (1)

Claim An analog-to-digital converter containing a voltage divider, a group of n, where η is the number of voltage quantization levels, EXCLUSIVE OR elements, a group of η comparators, the first inputs of which are combined and are the input bus, and the second inputs are connected to the corresponding outputs of the voltage divider, input which is the reference voltage bus, the outputs of the comparators are connected to the first inputs of the corresponding elements EXCLUSIVE OR and, except. the first, with the second inputs of the previous EXCLUSIVE OR elements, the second input of the last EXCLUSIVE OR element is a zero potential bus, characterized in that, in order to increase technological reliability. due to the uniformity of the structure, an n-bit ring shift and group register are introduced into it! of η AND-NOT elements whose outputs are combined and are the output bus, the first inputs are connected to the outputs of the corresponding bits of the ring shift register, and the second inputs are the corresponding buses of the Galois field code, the information inputs of the ring shift register are connected to the outputs of the corresponding EXCLUSIVE OR groups, and the first and second control inputs are respectively buses for * writing and reading. Comparator Output Code Output Code EXCLUSIVE OR Galois Field Code on Element Inputs AND NOT Codes on out. VTsP U _X = 7; U _X = 12 U, = 7 : and / "= 12 0 0 0 0. 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 r ° p 1010 0 i 0 0 1 ¹ 1 0 1 0 0 1 0 1 0 1 0 0 1 1 ¹ 1 I 0 1 0 0 1 1 1 1 0 1--' · - A 1 ΛΛ 1 ⁰ and 1 UU 1 1 0 0 θ 1 1 0 0 ! ^eleven 1 1 0 0 ⁰ 1 NN 1 1 0 0 0 1 1 0 0 0 1 1 0 0 ' 0