SU1282327A1 - Analog=to-digital converter - Google Patents

Abstract

The invention relates to the technique of analog-to-digital signal conversion and can be used in high-speed information-measuring systems where digital methods for processing analog information are used. The aim of the invention is to simplify the design and increase the speed of an analog-to-digital converter of a parallel-serial type by reducing the number of parallel converters used from four to three and using simpler devices and by performing correction of high-order errors (the result of the first conversion stage) at the same time with the conversion process in the second stage without extra time. The device contains parallel converters 1-3, D / A converter 4, differential signal amplifier 5, counter 6, comparator 7, trigger 8, differential signal amplifier 9, encoding logic device 10 with AND 11, 12, OR 13 elements, output register 14. 1 C .P. f-ly, 3 ill. / from €

Description

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11282327

The invention relates to the technique of analog-to-digital signal conversion and can be used in high-speed information-measuring systems where digital methods for processing analog information are used.

The purpose of the invention is to increase reliability by simplifying the converter and speeding up.

Figure 1 shows the functional diagram of the Converter; Fig. 2 shows the scales of the first and second stages of the transformations (in order to simplify the figure, the number of bits of the parallel ADCs used is assumed to be three - N 3); on fig.Z - timing diagram of the analog-to-digital converter.

The device contains voltage converters 1-3 in code, digital-to-analog converter (DAC) 4, first amplifier 5 of the differential signal

signal, device 10 encoding logic, consisting of the first 11 and second 12 groups of elements AND, groups of elements OR 13 and 2 N-bit dn output register 14. The cocking of these nodes allowed to exclude from the circuit of the converter (figure 1), except one N-bit ADC in the second stage, adder additional code

2

same polarity, t. e. (U.) Cho. To achieve this condition, an analog zero of the I transducer is fed into the initial offset,

equal u, p D quantum converter (figure 2). As a result of this, the code of the first conversion stage at the output always either has no errors, or there is a unit of the least significant bit in it. She ensures that the condition (and -) is met. O. At the same time, if in the process of conversion in the code of the first stage there is a loss of a low-order unit, then the output voltage

right bffO

the life of amplifier 5 will be

by

Shat level and „p z, ie, ,,. 2 .IUx - UtsAp

t, counter 6, comparator 7, trigger-, second amplifier 9 difference 20

25

The Ug value lies within the overflow range of the converter 2 (Fig. 2). In this case, the output of the amplifier 9 will be such a voltage that would be at the output of the amplifier 5 in the absence of a loss of the least significant unit, and the condition O is fulfilled. -and „,„ - и ,, р l2 ilJ

- tslg

 Mr

the voltage U has the value of, rGz; and is within the range of correct transformations of the converter 3 (Fig. 2).

If, in the process of conversion, there are no errors in the code of the first stage, then the voltage U will have a value.

in addition In addition, the introduction of new 35 range from zero to 2 (diaparentes and connections between them made it possible to correct errors in the code of the first conversion stage simultaneously with the Conversion process in the second stage without additional time costs, which increased the speed of the converter .

The device works as follows: ija3OM.

At the beginning of each cycle of operation, a coarse N-bit conversion of the input voltage is performed using the first converter 1 (the first conversion stage). The coarse conversion result (output code of the first conversion stage) with the help of a high-precision DAC 4 is converted into an analog signal, the difference from the known device in the differential voltage difference and, and always has one and

five

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2

same polarity, t. e. (U.) Cho. To achieve this condition, an analog zero of the I transducer is fed into the initial offset,

equal u, p D quantum converter (figure 2). As a result, the code of the first conversion stage at the output always either has no errors, or there is no unit of the least significant bit in it. She ensures that the condition (and -) is met. O. At the same time, if in the process of conversion in the code of the first stage there is a loss of a unit of the lower order, then the output voltage will be right

the life of amplifier 5 will be

by

Shat level and „p z, ie, ,,. 2 .IUx - UtsAp

0

five

The Ug value lies within the overflow range of the converter 2 (Fig. 2). In this case, the output of the amplifier 9 will be such a voltage that would be at the output of the amplifier 5 in the absence of the loss of the low-order unit, and condition O is satisfied. -and „,„ - и ,, р l2 ilJ

- tslg

 Mr

the voltage U has the value, gh, and is within the range of correct transformations of the converter 3 (Fig. 2).

If, in the conversion process, there are no errors in the first-stage code, the voltage U will have a value.

located within the 35 range from zero to 2 (range

five

zones of the correct transformations of the converter 2 in figure 2).

Thus, if in the conversion process in the first stage error code is missing, then the correct value of the amplified differential voltage takes place at the output of the amplifier 5, and if in the first stage code there is a loss of the least significant unit, then at the output of the amplifier 9. Therefore, obtaining The correct code for the second conversion stage in the proposed device consists in the simultaneous (parallel) conversion of the voltages of both amplifiers 5 and 9, respectively, by means of converters 2 and 3 and the selection of the correct and the output of one of them. The task of choosing the right code

5 of the second conversion stage, the comparator 7, the trigger 8, the first 11, and the second 12 groups of elements AND, the group of elements OR 13 are solved.

3

The second conversion stage starts from the moment of supplying control inputs to the control inputs of the control voltage converters 2 and 3. This moment corresponds to a time equal to t (conversion time of converter 1)

+ t (time of digital-to-analog conversion of DAC 4) + t to t (time taken by amplifiers 5 and 9 to amplify the differential input signal until a steady-state output voltage is reached) from the start of the conversion (FIG. 3)

The comparator 7, by comparing the output voltage of the amplifier 5, equal to (and - 2, with a threshold voltage equal to U 2), produces a control signal which, through the trigger 8, is applied to the inputs of the first 11 and second 12 groups of elements AND to make a selection the correct code for the second conversion stage, as well as to the summing input of the counter 6 for correcting the error code of the first stage, moreover, the correction is performed in the account simultaneously with performing the second conversion stage by adding the least significant bit to the code ervoy stage (fig.Z).

The corrected code of the first counter from the output of the counter 6 is fed to the output register 14 and forms in it the highest N bits of the output code of the converter. The selected correct code of the second stage from the output of the group of elements OR 13 is fed to the corresponding inputs of the output register and forms the lower N bits of the output code of the converter.

By the end of the conversion process, a 2 N-bit output code is generated at the output of the device (in the output register). This completes one conversion cycle. The total conversion time of the proposed device is shorter than the total conversion time, known almost to the execution time of the summation of the 2N-split of the binary code in the adder of the additional code. This circumstance leads to an increase in the speed of the converter.

Claims (2)

1. Analog-to-digital Converter containing the first transform Voltage code, the outputs of which through a digital-to-analog converter are connected to the first input of the first difference signal amplifier, the second input of which is combined with the input of the first voltage converter to the code and is the input of the second voltage converter to the code whose outputs are respectively connected to the first group information inputs of the encoding logic device, the second group of information inputs of which is connected to the outputs of the third voltage converter in the code, characterized in that th povpieni reliability by simplifying the transducer and povsch1eni speed, a comparator, a trigger, a second differential amplifier, an output register and a counter are entered into it, the digital inputs of which are connected respectively to the outputs of the first voltage converter into the code, the outputs are connected to the inputs of the upper bits of the output register, and the counting input is combined with the first control input of the coding logic device and connected to the forward output of the trigger, the inverse output of which is connected to the coding logic device and the input is connected with the output of the comparator, the first input of which is connected to the bus threshold; voltage, the second input is connected to the output of the first differential signal amplifier, the first and second inputs of which are connected respectively to the first and second inputs of the second differential voltage amplifier, the third input of which is the reference signal bus, and the output connected to the input of the third voltage converter code, and the outputs of the coding logic device are connected to the inputs of the lower bits of the output register, respectively. 2. The converter according to claim 1, characterized in that the encoding logic device therein is made on the first and second group of elements AND and the group of elements OR whose outputs are the outputs of the device of encoding logic, the first inputs are connected to the corresponding outputs of the first group of elements AND, l1 the first inputs of which are combined and are the first control input of the coding logic device, and the second inputs form the second group of information inputs of the coding logic device, the second inputs of the group of elements OR are connected with the corresponding 28323276 The first outputs of the second group of elements are And, the first inputs of which are combined and are the second control input of the encoding logic device, 5 and the second inputs form the first group of information inputs of the encoding logic device. e / 7 ffflcrj SL7u / 7 € M6 npeoSpo3o6 ( Time diagram paffo / 77e / / jfleff / rozaefioeo Time Time. YU- / 7fleoS- il -npeoff- .poxSof / t / j po3oSa M I / iy / 7 / I // 7 1I is  OMOHvoHi e npeofpcfooSoff / Fig 3