SU1441385A1 - Device for sorting numbers - Google Patents

Abstract

The invention relates to the field of computing and can be used in information retrieval systems and statistical data processing systems. The purpose of the invention is the extension of functionality due to the integral and differential distribution of numbers. The device contains an input register

Description

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5, polling register 3, memory block 6, adders 14 and 15, amount registers 16 and 17, subtractor 18, and controls. The next data packet through input register 5 arrives at the address input of memory 6, from which the number is read, and arrives at the inputs of the adder 14. This number is summed with the unit permanently located at the second input of this adder. The result is stored in the sum register 16 and then written to memory 6 at this address. Thus, in the memory block 6, the number of numbers sent to each of the address values from the next data packet is added. Information is polled through the polling register 3 in order, starting with a value of zero. At the address of the current poll number from memory block 6, the current value of the differential function is read. At the same time, the same value enters the inputs of the first group of the adder 15, where the Invention relates to computing technology and can be used in information retrieval systems and statistical data processing systems.

The aim of the invention is to extend the functionality due to the integral and differential distribution of numbers.

FIG. 1 is a diagram of the device in FIG. 2 is a diagram of a former mode.

FIG. 3-6 timing charts of the device.

The device comprises a clock pulse generator 1, a poll counter 2, a poll register 3, a cycle counter 4, an input register 5, a memory block 6. Trigger trigger 7, .elements OR 8-10, element 11, driver 12 immers, trigger 13 select register, adders 14 and 15, registers 16 and 17 sums, subtractor 18. 385

The result of the sum is cluttered on register 17 and then goes to the inputs of the subtracted subtractor 18. This sum is subtracted from the number equal to the number of numbers in the data packet. This is the current value of the integral function. After each interrogation of the current values of the differential and integral functions, zero is recorded in the memory cell of the block 6 from which it was polled. Thus, the differential distribution function shows how much About & the number of fixed values falls on one of the selected levels (repeatability function). The integral distribution function shows how much of the total number of numbers falls on the values above a given level (security function). 6 ill.

Shaper 12 pulses contains the element OR 19, the delay element 20, the element AND NOT 21.

The device works as follows.

Initial installation (see FIG. 3).

When initially turned on or when a negative signal of the initial installation of the LOW is given, trigger 7 of the initial installation is activated. The signal NU through the second element OR 9 zeroes the poll counter 2 and through the third element OR 10 sets the trigger 13 for selecting the register to enable the register 3 for polling, since the log 13 is set at the first output of trigger 13. 1. Swept the second release of the trigger 13 register selection log. ABOUT,

prohibiting the operation of the input register 5 (the register is in the high-impedance state, which corresponds to the state of an open circuit) and “d keeps the first

the sum register 16, the output of which is associated with the information input of the memory unit 6.

At the first output of the trigger 7 of the initial installation, a log, 1, is set up, which enables the operation of the generator of 1 clock pulses. The log of the second output of the trigger 7 of the initial installation via the And 11 element sets the block 6 of the memory to the recording mode.

The signals from the generator 1 clock pulses through the first element OR arrive at the counting inputs of the counter

2 polls and register 3 polls. On the front of the synchronization signal, information from the information output of the polling counter 2 to the polling register 3 is recorded, and by the decay of the same pulse, the information output of the polling counter 2 is increased by one. Thus, the information from the information output of the polling counter 2 through the polling register 3 arrives at the address input of the memory block 6, where the addresses of the cells starting from zero, and thus in the memory array, are sorted by the following clock signals from the clock generator 1. ty are written zeros. Block 6 of memory is reset. At the end of the memory zeroing cycle, a negative pulse is formed at the second output of the polling counter 2, which is 1M.1y the second element OR 9 sets the same counter to the initial state. The same signal resets the trigger 7 of the initial installation, which prohibits the operation of the generator 1 clock pulses. Also, the counter of 4 cycles and the trigger 13 for selection of the register are reset, at which the operation of input register 5 and the first register of the sum is allowed. Register

The 3 questions are set to a high pedal state. In the zeroed state, the second regis 17 is kept. The memory unit 6 is set to read mode and record information. On this training device

to work ends.

In the scheme, the first element OR 8 is controlled by high levels of input signals, the second element OR 9 and the third element IL 10 are controlled by low levels of input signals (OR zero).

The cycle of receiving information (see Fig.4).

The input INF information in the binary representation simultaneously with the sync pulses of the SI is recorded on the front C in the input register 5 and then goes to the address input of the memory block 6. The number of incoming numbers (data packet) determines the counter of 4 cycles, and this value is equal to N. The current -th number can take a value from O to M, i.e.

O AM, .-.

where a 1, 2, 3, N,

M is the maximum A; -e number (determines the amount of memory), N M.

From block 6 of memory at the address of the received value, the number is read (at the control input of block 6 of memory at the moment a positive potential), which is fed to the first

input (first current term) of the first adder 14 of the current number. This number is summed with the unit that is permanently located at the second input of the same sztflator (the second term). Further, by the decay of the SI signal, the result is memorized on the first register 16 and then on the negative potential supplied to the control input of the memory block 6,. It is recorded in the memory cell at the same address and in the same clock cycle of the SI sync pulse. Such a read-write mode at a given address in a given clock cycle is formed on the driver of 12 pulses through an element 11. Thus, in memory block 6, the number of numbers that came to every 1 of the address values, i.e. in block 6 of the memory, it is calculated how many numbers of one gradation are in the series of a given cycle.

Upon completion of the cycle of receiving and processing input information, the 4-cycle counter, counting the number of received values in the packet (N-values), generates a negative pulse, which through the third element OR 10 sets the first trigger output

13 select the register in the state of log.1, and the second output - in the state of the log.O. The work of the register of 3 surveys and the second register of 17 amounts is permitted. Input register 5 is set to high impedance state. In the zeroed state, the first sum register 16 is held, which is directly connected to the information input of the memory unit 6. The latter remains in read-write mode.

The survey cycle informational (see Fig.5).

By signal polling OPR through

the first element, OR 8, is included in the Dew parameter; the value of a single counter 2 poll is set. Through the poll register 3, information is read from memory block 6, which is implemented as follows.

When the first OPD signal arrives through the first element OR 8, the zero value is recorded in the polling register 3 on the signal front, since the poll counter 2 was reset to zero.

the cycle of receiving information and on its glob the 20th number with the first value of the differentiation Bcw informational output is currently zero. At this address, a value corresponding to the number of zero gradation numbers is read from memory block 6. This is the first value of the differential function. At the same time, the same value from memory block 6 is fed to the first input of the second adder 15 of the current number (the first current term). It is added to the number that is on the second input of the same adder (second current addend) At the second input of the adder 15 of the current number, the number zero is at the moment, since the second sum register 17 was reset to zero in the information receiving cycle. The result of the sum of the decay of the OPD signal is remembered.

on the second register 17 sums and post-40 differential and integral

It goes to the first input of the subtractor 18. At the subtractor 18, the received value of the sum is subtracted from the number N, which is permanently located at its second input (the number N by its value is equal to the number of numbers in the data packet). This is the first value of the integral function. In the cell of the memory block 6, from which the differential and integral values were polled, the zero potential is written down with a certain delay by the negative potential, because the first register of the sum in the given cycle (in the interrogation cycle) is zeroed directly connected to the information input of block 6 of memory. Thus, resetting this cell

functions for each signal OPD stupid to the input of the device with real printing. At the end of the polling cycle (polling cycle by

since it is equal to), a positive signal is generated on the controller that controls counter 2 of the poll, which, after inserting the OR 9 element, embraces itself. Counter 4 cycles also zeroes

gQ is set in formation reception mode. The trigger 13 for selection of regs is set to the position, the input register is working directly. Register 3 for polling information transmits to a high-impedance state. The device is ready to receive a data packet.

Thus, if you designate the number of numbers that

55

 The memory block 6 occurs immediately after the derivation of the differential and integral functions. Let us read-write at this address in a given clock cycle of the OPD signal, which forms the driver of 12 pulses. At the same time, according to the decay of the OPD signal in this cycle, at the output of the counter, 2 points Upon receipt of the second signal ODA on its front on the register 3 of the survey remembers the value of one. From block 6 of the memory reads the value corresponding to the number of numbers of the first gradation. This is the second value of the differential function. At the same time, the same value is summed up on the second adder 15 of the current

the main function, which is currently located at the second input of this adder, and after the decay of the OPD signal is stored on the second register 17 of the sum. The desired sum is subtracted from the subtractor 18. This is the second value of the integral function. The memory cell, as in the previous case, at this address in this

the clock of the OPD signal is zeroed using the read-write mode generated by the imaging mode 12. The decay of the second OPD signal at the output of the polling counter 2 is set to two. Similarly, the subsequent values of the differential and integral functions are obtained, and the cells of the memory block 6 are similarly zeroed. Cal | doe value

differential and integral

functions for each signal ODA is fed to the input device, followed by f printing. At the end of the polling cycle (the polling cycle is equal to the value), a negative signal is generated at the control output of the polling counter 2, which, through the second OR 9 element, zeroes itself. The 4 cycle counter also zeroes and

set in receive mode. The trigger 13 for the selection of the register is set to the position at which the input register 5 is operating. The register 3 for polling information goes into a high-impedance state. The device is ready to receive the next data packet.

Thus, if we denote the number of numbers that takes

A; - gradation through D, then the function D (A}) corresponds to the law of differential distribution

O (A,) D (A,)

and it shows how much of the total number of fixed values falls on one of the selected levels (repeatability function). The values of N 5-D (A |) are a function that corresponds to the law of the integral distribution

F (A;) N - XlD (A;) j,

e-i

which shows how much of the total number of numbers falls on the values of the specified level

(security function).

Pulse generator 12 is shown in FIG. 2. The pulse shaper 12 operates as follows (see FIG. 6).

At the first or second input element 19 pulses arrive. From the inverting output of this element, the signal goes to the first input of the NAND 21 element. From the non-inverting video element 19, the signal goes through the delay element 20 to the second input of the AND-21 element. A pulse log is generated at the output of the AND-21 element. Oh, which is somewhat delayed in relation to the input signal decay. A read-write signal is generated, which is fed to the control input of memory block 6.

Thus, on the front of the signal si or opr, by the positive potential at the control input of the memory block 6, the information is read, by the decay of the si signal or opp on the potential log. The information is stored in memory, i.e. in one clock cycle of the input signal, the signal is switched Read-write of the memory block 6.

Claims (1)

Invention Formula A device for sorting numbers, comprising a clock pulse generator, a poll counter, a memory block, two addition blocks, an AND element and an OR element, characterized in that, in order to expand the scope of application by means of an integral and Yu ,five 20 25 ZO 40 45 50 gg 383 " differential distribution of numbers, it contains: it is the initial setup trigger, two G1I elements, a register selection trigger, two sum registers, a subtractor, a loop counter, an input register, a polling register, a pulse shaper, and the setup input for the initial trigger trigger is the input of the initial installation of the device and is connected to the first inputs of the first and second elements OR, and the direct output is connected to the start input of the clock generator, the output of which is connected to the first input of the third element nta OR, the second input of which is the polling input of the device, and the output is connected to the first input of the pulse generator, with the synchronous inputs of the polling counter, polling register and the first sum register, the bit outputs of which are connected to the inputs of the readable subtractor and the inputs of the first group of the first adder the sum of the outputs of which are connected to the information inputs of the first register No. and the inputs of the second group are connected to the information outputs of the memory block, the outputs of the differential distribution of device numbers and the inputs of The soil of the second adder, the inputs of the second group of which are the inputs of a given number of devices, and the outputs of the sum are connected to the information inputs of the second sum register, the outputs of the bits of which are connected to the information inputs of the memory unit, the control input of which is connected to the output of the element And, the first input of which is connected to the output of the pulse generator, and the second input with the inverse output of the initial setup trigger, the input of the installation in O of which is connected to the second input of the first element OR, with the output overflow Neither the polling counter from the input 1 of the installation to the zero state of the cycle counter and the trigger of selection of the register, the installation input in its single state is connected to the output of the second OR element, the second input of which is connected to the overflow output of the cycle counter, the counting input of which is the synchronization input device and is connected to the second input of the pulse generator, with the synchronization input the input register and with the synchronization input of the second sum register, the input of the setting to the zero state of which is connected to the input of the installation to the zero state of the input register and the inverse output of the register selection trigger, the direct output of which is connected to the inputs of the installation to zero the state of the polling register and the first sum register, the inputs of the decrement subtractor are the inputs of the constant 13 Phie.g t t  Ht eipet values the device, and the outputs of the integral distribution of the device numbers, the information inputs of the device are connected to the information inputs of the input register, the outputs of the polling counter bits are connected to the information inputs of the polling register, the bits of the input register and polling register are connected to the corresponding address inputs of the memory block. 21 / Lj 2 f (Sx. ogp 1 W y 6 (6x. ex.) RJNJ 6 (8h.don.} Skz ZXS2 13 {Ex.1); 13 (by.2) "(Sux.) 1 If not mem value FIG L 6 P  s SI g 1 ii | .four one