SU1501039A1 - Device for sorting information - Google Patents

Abstract

The invention relates to computing and can be used in information processing systems. The aim of the invention is to expand the scope. The device contains synchronization unit 1, counter 2, memory unit 3, switch 4, registers 5 and 6, trigger 7, comparison circuits 8 and 9, element ZI-2, OR 10. DEVICE RELEASES DELIVERING NUMBERS, DETERMINING THE MAXIMUM AND MINIMUM NUMBER AND HANDLING NUMBERS IN ORDER OF AGE OR DEPRESSION. 5 IL.

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The invention relates to computing and can be used in information processing systems.

The purpose of the invention is to expand the scope.

Fig, 1 shows a functional diagram of the device; FIG. 2 is a functional diagram of a synchronization unit; FIG. FIGS. 3-5 are timing diagrams of the device operation: FIG. 3 — operation in input and output modes; 4 - the operation of the driver in the block synchronization; FIG. 3 shows the operation of the device in the output mode in more detail.

The device contains (FIG. 1) synchronization block 1, counter 2, memory block 3, switch 4, registers 5 and 6, trigger 7, comparison circuits 8 and 9, element 2I-OR10, control inputs 11-13 of the device, clock inputs 14.15, information input 16 and output 17, control outputs 18.19 of the device.

Input 11 receives a signal to set the input mode RECEPTION. At input 12, the signal sets the output mode to OUT. On input 13 is the signal to set the direction of sorting. AGE. The input 16 receives the g-bit code of the sorted number, and the sorted numbers are read by the g-bit output 17, followed by the ID STROB OF EXTRACT at output 19. From output 18, the indication of the end of output is removed.

From the first outputs of the comparison circuits 8.9, the equal signal of the input operands is removed. From the second output of the circuit 8, the comparison is a signal; from the second output of the circuit 9, the comparison is.

The synchronization unit 1 contains (FIG. 2) elements 2I 20-22, 2STI 23, 24, ZI-HE 25.26 and shapers 27, 28 pulses, which contain trigger 29 and element 2 and 30. At the first inputs of shapers 27.28 sync pulses are received from the inputs of block 1, 1.4.1.5, respectively, to the second, the signals for setting modes and inputs, respectively, 1.2.1.1.

On fig.Z marked: a - sync pulses T1, arriving at the input 14 of the device; b - T2 clock pulses at input 15; c - signal of the reception mode at input 11; g - register setting signal 5.6; d - signals of installation of the counter 2; e - synchronization output of block 1; W — recording signals to memory block 3; h - signal setting mode Issue at input 12; and - signal modification counter 2; k is a sign of the end of dispensing at exit 18. Additionally indicated: I - receiving data into the device; TI - issuing sorted data.

In figure 4, the following is indicated: a — sync pulses on the first inputs of the formers 27.28 of the synchronization unit 1; b - mode signal at the second input of the imager; in - inverse trigger trigger 29 of the driver; g - the output of the driver.

In figure 5 are marked: a, b - sync pulses T1, T2; in - signals of modification of the counter 2; g - output of memory block 3; d - recording signals in block 3; e - identification signals Strobe issuance at exit 19.

The device works as follows.

The inputs 14, 15 enter the clock-shifted pulses 11, T2 that are out of phase relative to each other in the device (Fig. Per, b). The input mode is set by the receive signal by setting the level T at input 11 (FIG. 13). At the same time, the input 12 is set to O, and the input 13 is in a state depending on the direction of ordering. By level 1 at input 11, switch 4 connects input 16 to the information input of counter 2, while at input 12, element 10 blocks the output at output 18 of the end of discharge feature.

The Receive signal arrives at D - the trigger input 29 of the driver 28 (Fig. 45) and through element 2I 30 - at the output of the driver.

The sync pulse T2 arrives at the first input of the imaging unit (Fig. 4a) and, on its negative front, at the output 29, O is set (Fig. 4c). Thus, the element 30 of the imaging unit 28 generates at the output of the unit 1 a pulse (FIG. 4d), setting the register 5 to zero, the register 6 — to one state (FIG. 3g).

According to the sync pulses T1, coming through the input 14, the elements 2I-20 and -. 2IL 24 to the block installation block 1, numbers are entered into the counter, inputted to input 16 (FIG. 3) via T2, fed through element 2 and 21 to the recording output of block 1 (FIG. 15) to block 3 by the addresses, corresponding so515

This is also the case of counter 2, entered 1, set up and in the information input of block 3. On the dir of the registers 5,6

12 enter through the element 2 and 22 and the synchronization output of block 1 (fig.Ze)

The state of counter 2 is compared by comparison circuit 8 with register 5 status and register 6 comparison circuit 9. If the first of 16 numbers received at the input does not represent a single or zero code, then the recording resolution signals, which both comparison circuits generate to their second outputs, and on T2 this number is carried in both registers. If the values of the next numbers exceed the value of the number entered in the register 5, they will be recorded there. If these numbers are less than 6 entered in the register, they are entered into it. Meanwhile, at the end of the input operation in register 5, the maximum number of entries in the list being ordered will be stored, in register 6 - the minimum number.

After transmitting the entire list to the device, the Receive signal is reset. Element 20 blocks receipt of T1 at the input of the installation of the counter 2, elements 23.21 block receipt of T2 at the input of the record of block 3, element 22 is the receipt of I2 at the synchronous input of registers 5,6. Switch A disconnects from the information input 16 counter 2.

If the input mode 13 - 1 sets the sorting mode in ascending order, the output of register 6 is connected to the information inputs of counter 2. If the input 13 - O is set to descending sorting, register 5 is connected.

The output mode is set by the Output signal — by setting 1 at the input

13 (fig.ZZ). Element 10 connects to output 18, depending on the signal. Increasing the first output of comparison circuits 8 or 9. Lasing device 27, using pulse T1, produces, as for shaper 28, a pulse arriving through element 2A of unit 1 to the setting of counter 2 (FIG.

Ii) The meter sets the maximum or minimum number of spikes. Then the counter is modulated by pulses T1 (Fig. 3i). In the presence of a signal, the increase in T1 is received through the element ZI-NOT 25 and the code of block 1 for summation of the input of the counter, in the absence - through the element ZI-NOT 26

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and the output of block 1 is pa pychitm1 11chi | (phog;. memory block 3 is selected by the pg state of the counter (fig.5 n, iO. Scntyg1any.g from block 3.1 (fig 5e) pzn, t; smt that given addr The read from the list corresponds to the number from the list, and a trigger 7 is set at T2 - the identifier of the number transmitted from the counter to output 17. The trigger 7 is reset with the next T1 (FIG. 5e).

Elements 23, 21 allow passage of T2 to the input of the record of block 3. After reading the information from block 3 into it at the current address, O set at the information input of block 3 is entered — memory is cleared (Fig. 5 g, e).

When the list is normalized ascending, counter 2, sequentially switching, will be set to the value of the maximum number of the list. At the first output of the comparison circuit 8, it will be set 1 and at the output 18 - a sign of the end of dispensing. At normalization in descending order, the termination feature will come from the first output of the comparison circuit 9 (FIG. 3k). On this basis, the Issue signal is reset, the arrival of T T through elements 25 or 26 and T2 after 21 is blocked.

When power is turned on, memory cells and registers are set arbitrarily. Therefore, for the initial installation nx, it is necessary to perform a preparatory I / O cycle. In the input mode, a zero code is entered into the device, which is entered into register 6 by the HF, then a single entry into register 5. In the output mode, counter 2 sequentially generates all its conditions and all O 3 is entered into O. After that, the device is ready for operation .

This means that the memory of the incoming list of numbers, the determination of the maximum and minimum number in the list and the resolution of the normalized list in order of decreasing or increasing. At the same time, the memory is not polled completely, but only in the list interval, which improves speed devices. form. of invention

A device for sorting information comprising a counter, a synchronization unit, a memory unit, an address input

which is connected to the counter discharge bits n is the information output of the device, and the recording input is connected to the recording output of the synchronization unit, the clock input, the first and second control inputs of which are the clock input and the input and output inputs of the device, that, in order to expand the scope of application due to the possibility of sorting in a certain range, a switch has been entered into two registers, two comparison circuits, a trigger, a 2I-OR element, the output of which is the output of a sign The device output, the first inputs of the first and second elements AND element 2I-OR are connected respectively to the outputs equal to the first and second comparison circuits, the second inputs of elements AND element 2I-1Ш11 are connected to the second control input of the synchronization unit, and the third input of the first element AND element 2I-OR is connected to the inverse of the third input of the element AND of the element 2I-OR, the first control input of the switch, the third control input of the synchronization unit and the input Device increase, the clock input of the device is connected to the reset input the trigger, whose input is the output of the strobe of the device, and the information input is connected to the output of the memory block, the information

the input is connected to the first control input of the synchronization unit and the second control input of the switch; the first, second and third groups of information inputs of which are connected respectively to the information inputs of the device and to the output bits of the first and second registers; the output bits of which are connected respectively to the first groups of inputs of the first and second comparison circuits; the second groups of cat / era inputs are combined with the information inputs of the first and second registers and with the bits of the counter, the second clock the device input is connected to the trigger trigger input and the second clock input of the synchronization unit, the outputs of setting the counting mode and setting the counter of which are combined respectively with the inputs of the addition, subtraction and initial installation of the counter, the information inputs connected to the outputs of the switch bits, the initial output the installation of the synchronization unit is connected to the inputs of the installation in the zero state of the first and in the single state of the second register, the enable inputs of which are connected respectively to the outputs of Bo Less than the first, and Less than the second comparison circuit, and the sync inputs are connected to the sync output of the sync block.

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Claims (1)

claims A device for sorting information containing a counter, a synchronization unit, a memory unit, the address input of which is connected to the outputs of the bits of the counter and is the information output of the device, and the recording input is connected to the recording output of the synchronization unit, the clock input, the first and second control inputs of which are respectively, the clock input and the inputs of the reception and the device, characterized in that, in order to expand the scope due to the possibility of sorting in a certain range, into it a commutator, two registers, two comparison circuits, a trigger, an II-OR element, the output of which is the output of a sign indicating the end of device delivery, are entered, the first inputs of the first and second elements AND of the II-IPI element are connected respectively to the outputs equal to the first and second circuits 20 for comparison, the second inputs of the AND elements of the 2AND-OR element are connected to the second control input of the synchronization unit, and the third input of the first AND element of the 2AND-OR element is connected to the inverse 25th third input of the AND element of the 2AND-OR element, the first control input of the switch, the fourth control input of the synchronization block and with the input Increasing the device, the clock βθ input of the device is connected to the reset input of the trigger, the input of which is the output of the output gate of the device, and the information input is connected to the output of the memory block, the information input of which is connected to the first control input of the synchronization block and the second control input of the switch, the first, second and third groups of information inputs of which are connected respectively to the information inputs of the device and to the outputs of the bits of the first and of two registers, the outputs of the discharges of which are connected respectively to the first groups of inputs of the first and second comparison circuits, the second groups of inputs of which are combined with the information inputs of the first and second registers and with the outputs of the bits of the counter, the second clock input of the device is connected to the trigger sync input and the second clock input synchronization unit, the outputs of the job mode counting and setting the counter which are connected respectively to the inputs of the installation of addition, subtraction and initial installation of the counter, information inputs of the input, which is connected to the outputs of the bits of the switch, the output of the initial installation of the synchronization unit is connected to the inputs of the installation to the zero state of the first and to the unit state of the second register, the permission-recording inputs of which are connected respectively to the outputs More than the first. and Less than the second comparison circuit, and the sync inputs are connected to the synchronization output of the synchronization block. FIG. I I 50103 9