SU1439572A2 - Number comparator - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to expand the field of application by providing a numerical analysis of the characters. The device contains the decoders (k number of analyzed numbers) 1 1 ", a group of elements OR 2, -2„, an analysis unit 3, an encoder 4, a group of elements 5 and 6, - 6, a group

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elements OR-NOT 7, -7j, elements AND-NOT 8.9, OR-NOT 10.11, OR 12, 13, element AND 14, mode selection input 15, information inputs 16, outputs 17 (j- Numbers arrive in direct code with a sign to the inputs 16 - 16. Depending on the specified type of extremum and the presence among the analyzed numbers, positive or negative (which is revealed

The invention relates to automation and computer technology and is an improvement to the device auth.St. No. 1293726.

The purpose of the invention is to expand the scope of application by providing a number analysis of numbers, taking into account the sign of the words.

The drawing shows a diagram of the device.

The device contains a group of k decoders (kl is the number of analyzed numbers) 14-1ts, a group of elements OR 2, -2, an analysis unit 3, an encoder 4, groups of elements AND 5, -5 and 64-6k, a group of elements OR NOT , elements AND-NOT 8.9, SH-NOT, 10.11, ShSh 12.13 and And 14, mode selection input 15, informational inputs 16c - 16, where n is a copy of the digits of the analyzed number, and 16 - sign input, the rest are the inputs of the mantissa of the j-ro number (J 1,2 ..., k), outputs 17, –17 digits; a divided number.

 The device works in the following way.

The numbers to be compared (in the direct code with a sign; zero means a positive sign) go to the inputs

I k I6g -16у,. Input 15 receives a single signal if it is necessary to divide the maximum number, and a zero signal if it is necessary to select the minimum number.

If at the allocation of the maximum number among the numbers there is at least one, the sign bit of which is zero (i.e., a positive number), then at the output of the AND-HE element 8 is one.

1439572

T-8 and N-10 (10) destroys the conversion from binary to unitary of those numbers that may be required, the analysis block searches for either the largest or the smallest in absolute value number, which is then converted by the encoder. in binary code and arrives on phases 17. 1 Il.

which leads to the establishment of a zero signal at the output 1 of the device (a sign output, that is, the maximum number is positive). A single signal will also be at the outputs of the elements AND 14, OR 13 and those elements AND 6 that correspond to negative numbers A. These single signals are sent to the corresponding elements OR NOT, and zero signals from these elements will close the corresponding decoders 1. The remaining A5 numbers will be converted by decoders 12 into unitary codes, of which the analysis block 3, to the control input of which receives a single signal from the output of SHIII-13, will be allocated the leftmost (i.e. maximum). This value will be converted by the encoder 4 from unitary to binary code and the maximum number of mantissa will go to the outputs 17-17 of the device.

If during the selection of the maximum number all numbers turn out to be negative, then a zero value will be formed at the output of the AND-NE 8, AND 14, S1I 13 and all AND 6 elements. Therefore, the unit value will be at the outputs of all the OR-NOT 7 elements, and in block 7 analysis will select the rightmost number from. all numbers (i.e. a negative number with the smallest absolute value of the mantissa). At the exit of the 17d unit. When minimizing the number, the device operates in the same way, using the signals at the outputs of elements SH-HE 10, 11 and I 5 °.

Claims (1)

Claim The device for comparing the numbers according to the authors, no. 1293726, is valid so that, in order to expand the field of application by providing an analysis of numbers with signs, the first and second groups of k elements AND each, where k is the number of analyzed numbers, a group of k OR elements OR, NOT two elements, NEF two elements, NIP NIE, two OR elements and the AND element, and the input is the sign bit j of the device number, where, 2, k, is connected with the inverse input of the j-ro element of the AND group of the first group, the first input of the j-ro element of the AND group of the second group and with the j-we inputs of the first el elements AND-NOT and SHSh-NOT, the input of the device mode selection is connected to the first inputs of the AND element, the secondary OR-NOT element and the first OR element, the output of which connected to the first input of the second NAND element, the output of which is the output of the sign bit of the allocated device number, the output of the first AND – NE element connected to the second inputs of the second NAND element and the AND element whose output is connected to the second inputs of the AND elements the group and the first input of the second element OR, the output of which is connected to the control input of the analysis unit, the output of the first element OR — NOT to connect jieH to the second inputs of the first element OR and the second element — OR — NOT whose input is connected to the terminal input element s of the first group and the second input of the second element OR, the outputs J-X of the elements of the first and second groups are connected respectively to the first and second inputs of the j-ro element OR-NOT group, the output of which is connected to the gate input j-ro of the decoder