SU1429323A1 - Decoder of codes presented in residual-classes system - Google Patents

Abstract

The invention relates to computer and computer engineering and can be used in data transmission equipment operating with residual class system codes. The purpose of the invention is. reduction of equipment. This goal is achieved by the fact that a device for decoding codes represented in the system of residual classes, containing a memory block 15, an adder 32, a counter 8, multipliers 23, 24, and registers 7, 19, contains elements 1, 13, 21, 22, 26, 28, 30 delays, And elements 2.9, counters 10.11 triggers 3.25, decoders 14.16, groups of registers 17,18, register 27, block 20 for calculating the coefficient and the element OR 29 with the corresponding values wm. 1 hp f-ly, 2 silt, §

Description

 -

Set

fiiZ.

Yu

to with

N3

WITH

The invention relates to automation and computer technology and can be used in data transmission equipment that operates with residual classes (SSC) codes.

The aim of the invention is to reduce the amount of equipment.

Fig. 1 shows an iSciTBa scheme for decoding the codes represented in the SOC; in fig. 2 - I diagram of the coefficient calculation unit. The device (Fig. 1) contains a delay element 1, an AND 2 element, a trigger | 3, a device information input 4, an I setting 5 and a clock 6 device inputs, a register 7, a counter 8,; an I element 9, counters 10 and 11, an input ; 12 start the device, the element 13. For; holders, the decoder 14, memory block 15: ty, decoder 16, groups of registers 1 17 and 18, register 19, block 20, calculate the first factor, elements 21 and 22: delays, multipliers 23 and 24, trigger: 25, delay element 26, register 27, 1 delay element 28, element ШШ 29, ;; the delay element 30, the output 31 of the device operation end, the adder 32, the output 33 of the device result, the information output 34 of the coefficient calculation unit 20, the delay elements 35 and 36.

The coefficient calculation unit 20 (FIG. 2) contains a multiplexer 37 and 38, a computation output 39 output of unit 20, elements NOT 40-48, triggers 49-52, delay elements 53-63, elements OR 64-72, counters 73- 75, adders-subtractors. 76-78, circuits 79 and 80 comparisons, elements AND 81-97, registers 98 and 99.

Adders 32, 76-78 can be performed on the chip KR 1802IM1. The adder has the informational informational inputs, four inputs for receiving numbers from the corresponding information input, four control inputs for operations on numbers (addition or subtraction), information reception permission input, output output resolution input, information output, output equality of the result to zero output of the result sign. Moreover, each information input has its own input of the reception direction and its own control input of the operation.

If logical 1 is fed to the input of the receiving direction, then information from a certain input at arrival

The pulse at the receive enable input is written to the adder. If logical 1 is fed to the control input of the operation, then the corresponding number is written to the adder with a + sign, and if it is a logical O, then with a - sign.

In the device (Fig. 1), the decoding principle is applied, which is based on the sequential positional transformation of the number A according to the formula

And a ,, +. .. ..,

where m; (, N) - modules of the system; a, oi. ;

but. - coefficients calculated as follows: (oi; - modulo m - deduction)

L llSiiSl-iblSi

 sh,

where L is 0,1, .2, ... is matched with

smaller value and such that aj has integer value.

Coefficient a; is calculated as follows (, 4 ...);

but.

  J-Hi IbilSi.

mi

 3 filSi.i.Slii; i5i

m,

at

I Ll rSi: ii ± Li: 1.5x

m;, i

If we exclude any QC of residues, then the coefficients a, corresponding to these residues, are not calculated, and modulated, which correspond to them in the calculation, do not take part. This principle of sequential decoding allows decoding at a rate of arrival of deductions about (;.

Block 20 calculates the coefficient a; and works as follows.

The delay element 53 delays the input pulse by the trigger response time 49. Elements 54 and 55 a delay delays the input pulse by the response time of the adder 76, the delay Element 56 delays the input pulse by a time equal to the total response time of the counter 73 and the comparison circuit 79. The delay element 57 delays the input pulse by the time it takes to switch the trigger 50.

29323;

If the value of the number is zero, then the output of the equality of the result to zero of the adder 76 is set to a single signal, allowing the pulse to pass through the AND 81 element. From the last output, the pulse arrives at the second input of the OR 72 element and the third input of the OR 71 element.

The delay elements 58 and 59 delay the dead pulse of the OR element 72 of the set pulse for the response time of the adder 77. The delay element 60 delays the input pulse for the switching time of the trigger 51. The elements 61

and 62 delays delay the input im- 15 counter 73, set to pro

pulse at the time of the operation of the adder 78. The delay element 63 for; a; It holds the input pulse for the switching time of the trigger 52. The pulse from the start input at the initial moment of operation of the device 73, the comparison circuit 79 and the element switches the counters 73 and 74 and 99 The zero state, arriving at the input of the first control pulse at the output of the counter 74, manifests HE 42.

Thus, at the outputs of the counters 73 and. 74 The unit number code appears. Formed by the circuit, compared the code of the number one, the trigger 49 of the mouth 25 is not a single signal enters the

it returns to the zero state, which permits the reception of information into the adder 76 from the first information input and prohibits the reception of information arriving at its third information input. The delay time of the control pulse is received by dego at delay element 53, not less than the time of triggering trigger 49. From the output of element 53, the delayed pulse arrives at the input of element OR 64 and, having passed through it, at the input of delay element 54 and the enable input-reception of adder 76, writing information to the adder 76 from its first and second information inputs. The pulse from the output of the delay element 54 is fed to the input of the delay element 55 and the resolution input of the result of the adder 76, thus, at the time of the end of the pulse at the output of the delay element 55, the value of the number equal to the difference of the number received from the output 55 the input s ;, and the numbers received through the multiplexer 37 from the input ai ,, i.e. o / aa At the outputs of the sign of the result and the equality of the result to zero, the corresponding logic potentials are established. .

From the output of the element 55 delay pulse arrives at the inputs of the elements And 81 and 84.

casts the register 99 to the zero state, the output of which is the output of block 20. From the output of the element OR 71 pulses is fed to the counting input

the output of the code is the number one, and also enters the input of the element 56 of the delay-ki, with a delay time of not less than the total time of operation of the counting HE 42.

Thus, at the outputs of the counters 73 and. 74, the code for the number one appears. Formed by the scheme of comparison of the HE 42 element and the AND 86 element, allowing the pulse to pass from the output of the delay element 56 through the AND 86 element and the OR 65 element to the input

resetting the counter 73 and the output of block 20, which is a sign of the end of the calculation of the coefficient a.

Thus, if the difference ci -a, is equal to zero, then the coefficient

Consider the operation of block 20, in the case of. chge, when otj-a, e 0.

At the output of the equality of the result to zero, the adder 76 establishes a zero signal and, accordingly, a single signal in the code of the HE element 41, which is fed to the inputs of the elements; And 82-84. Thus, the pulse from the output of the delay element 55 through the element 81 does not pass, but enters through the element 84 and 84 to the input of the element 57 of the delay and the installation input of the trigger 50 and sets it to the zero state. The zero signal from the output of the trigger 50 is supplied to the second and third inputs of the receiving direction of the adder 77, and the single signal is given by. stupid at the first input of the reception direction of the adder 77. The impulse from the output of the delay element 57 passes: through

the element OR 66 is fed to the input of the element 58 of the delay and the input of the resolution and reception of the adder 77. The information received at the first information input of the adder 77 from the information board is 514293236

of the adder 76, is written to the sum-If / s, -a /

Consider the operation of the block for the following cases:

mater 77 and through the speMerai period equal to the delay time of the delay element 58, appears on the information output of the adder 77. From the output of the delay element 58, the pulse arrives at the input of the resolution of the result of the summer 77 and the trigger setup input 60. the trigger output | 50 is set to a single signal, the inverse output is the zero signal. As a result, the adder is prepared, nm, and 0.

51. od, j, - a, O.

In this case, a single signal from the output of the And 82 element is fed to the second inputs of the And 88 and 89 elements. 10 Value / odj h, / goes to the torus 77 k from its information output is fed to the input of the comparison circuit 80, to the other input of which the value module from the input block. In this case, a single signal from the output of the element And 82 is fed to the second inputs of the elements 88 and 89. 10 The value of (odj 3, / goes to the torus 77 k from its information output is fed to the input of the comparison circuit 80, to another which entry is a post; the value of the modulus from the input blockH for subtracting the number of hectares; is received by entering the information input sum-) 5ka 20. At the first output of the circuit 80

and 77 of the third informational comparison, single block 20 of the number appears, received-cash if / about-a, /. t on her second

go to the second information input from the output - if a, / t, and to

adder 77 output. The difference in eC-a Third of the comparison circuit 80 is one can be positive, the minus-20nich signal appears if

yoy or equal to zero. If about (, -a, 0, / oij - a, / i w-.

The output of the sign of the result is Let / 0 (a e, / ha, then a unit sig is set to 76 — the first input of the AND 88 element is fed on a signal that appears at the output of a single signal. The pulse from the output of the AND 82 element. So as at the output of the 25-element delay 59 through the elements of the ment NOT 40 a zero signal, then the zero 88 and OR 66 enters the evil signal is also at the output of the element .58 the delay and the resolution output And 83. receiving an adder 77, in which -a O, then the single signal operation a, / t.

The signal appears at the output of the AOR element. The output pulse of the element 58 is delayed by I83, and the zero signal at the output of the electric element provides the output of the output of And 82. reading to the information output of the sum of the calculation of the coefficients aj of the math 77. This same input pulse - it is necessary to carry out the calculation singing on the setup input of the trigger 50,

module ha. This process involves confirming the fact of operation of the adder 77

in subtraction mode.

If the result of the increase is greater than the value of p2, then the subtraction operation is repeated, i.e. pulse from the output of delay element 59 again

40

the elements are HE 43-46, the trigger 50, the delayed cops, the elements OR 66 and 68, the adder 77, the comparison circuit 80, the AND elements 87-91, 93 and 94 and the register 98.

If oLgi-a, O, then the calculation («tj.-a,) niodm.2 is performed by subtracting t from ui-i a, as long as the result obtained is positive, but less than T-, i.e. condition is met

. 0 (,) - pga, m ,,.

enters the enable input of the adder 77. This process continues until the condition is met

 a I - pshd rag.

g. 2. The value of / ut-a, /, from which the subtraction is made t, is completed until the following conditions are met

t „:

t ,, tPPust / odz - a, / - pt, yes a single signal from the second output If (oij-a,) - pga t then. Comparison circuits 80 are fed to the first- When the result of cr - a, O is the computational input of the element And 91. An impulse with

the output of the delay element 59 is fed to the second input of the AND 91 element and from its output is fed to the first input of the OR 72 element and the second input of the OR 71 element. A pulse from the output of the OR 72 element sets the register

55

// utj, -a, / - nmj / cii-a, / nm-i 0.

99 to the zero state, and the pulse from the output of the RSH 71 element goes to

that block for cl

- nm, and 0.

51. od, j, - a, O.

In this case, a single signal from the output of the And 82 element is fed to the second inputs of the And 88 and 89 elements. 10 Value / odj h, / goes to the torus 77 k from its information output is fed to the input of the comparison circuit 80, to the other input of which the value module from the input of the block) 5ka 20. On the first output of the circuit 80

t.

enters the enable input of the adder 77. This process continues until the condition is met

 a I - pshd rag.

t ,, that go on perls with

99 to the zero state, and the pulse from the output of the RSH 71 element goes to

the anevjeHTa 56 input of the delay and the counting input of the counter 73; In the latter, a unit is recorded, a single signal appears at the output of the comparison circuit 79 and the output pulse of the And 86 element of the counter 73 is zeroed. At the output of block 20, an impulse appears indicating that the calculation of the coefficient g is completed, and a 0. The operation of this part of block 20 is already indicated,

Let / sbg-a, / - pga j ha

g

tog out

yes a single signal from the third

The comparison circuit VO arrives at the first j of the above three conditions (1), the zero input of the element AND 89, the third input of which receives a pulse from the output of the delay element 59. This pulse passes through the element AND 89 and through the element OR 68 arrives at the input of the register decision record time-20, in which the number entered at its information input from the information output of the adder 77 is recorded.

The pulse from the output of the element OR 68 is a sign that the calculation of the value of / o6j-a / modulo mn is complete, and the result is written to register 98.

2. OBG - a, “with O,

In this case, a single signal from the output of the element And 83 is applied to the inputs of the elements And 90 and 94.

Calculation of the value

the signal from the output of the element And 90 passes through the element NOT 45 and to the first. input element And 94 is given a single signal. The second input of the And 94 element receives a pulse from the output of the delay element 59, and its third input is a single signal if (oij-a,) i О, at the fourth input is a single signal when / otj & 25 -nmj /

At. the fulfillment of all these conditions impulse s. the output element 29 delay; Ki passes through the element And 94 and enters the input element OR 66 and the adder 77 again continues the computation. This continues until tex until condition (1) is satisfied,

thirty

oda to

If // otj - a, / -, then the second output of comparison circuit 80 is set; 1 a single signal is impressed, and the pulse from the output of delay element 59 passes through AND 91 and enters the inputs of OR elements 71 and 72. In this case a 0. The work of this part of block 20 is reviewed. Thus, computing a, / im

module tn ends when three conditions are met

oti - a, o;

/ eit-, / - pshg 0; (1)

// WB 1 / PGG /: ™ 2

The decoding of these conditions is performed by the element AND 90. When vLi - a,: O, a single signal is sent to the third input of the element 90. With a, / - .O, zero signals are set at the outputs of the sign of the result and the result being equal to zero of the adder 77. Through the HE elements 43 and 44 these signals are fed to the inputs of the And 87 element, and if the condition is met, a, / - nm O output Element And 87 A single signal appears at the first input of Element And 90.

If the condition I, I -nm, j I mj is fulfilled, then a single signal C of the output of the comparison circuit 80 is fed to the second input of the AND element 90.

ten

but

As a result, a single signal from the output of the AND 90 element arrives at the first input of the AND 93 element, the second input of which receives a pulse from the output of the delay element 59, which passes through the AND 93 element, is fed to the second input of the OR element 68 and, having passed through it, records information from the output of the adder 77 to the register 98. This pulse is a sign of the end of the calculation of the value of otj. - a, modulo t.

At default of at least one

of the above three conditions (1), zero

the signal from the output of the element And 90 passes through the element NOT 45 and to the first. input element And 94 is given a single signal. The second input of the And 94 element receives a pulse from the output of the delay element 59, and its third input is a single signal if (oij-a,) i О, at the fourth input is a single signal when / otj & -nmj /

At. the fulfillment of all these conditions impulse s. output element 29 delay; Ki passes through the element And 94 and enters the input element OR 66 and the adder 77 again continues the calculation. This continues until tex until condition (1) is satisfied,

35

40

45

If // otj - a, / -, then the second output of comparison circuit 80 is set; 1 a single signal is impressed, and the pulse from the output of delay element 59 passes through AND 91 and enters the inputs of OR elements 71 and 72. In this case a 0. The work of this part of block 20 is reviewed. Thus, computing a, / im

it is finished.

one

Having the value a, / t, the coefficient a is calculated by the formula

. (

50

m,

where N 0,1,2, ...

55

Immediate deletion and subtraction are replaced by addition and subtraction operations. The following algorithm is implemented.

1. From the value of / ot - а, / П) is subtracted t, as many times as the difference becomes negative.

2. Ha is added to the subsequent difference so many times until the sum becomes positive.

3. Then, over the received positive amount, operations are performed.

(Sections 1 and 2), i.e. subtraction t, sum per ha. This continues until the result of the subtraction or summation is

will become zero.

j A. The total number of subtraction operations is calculated, and as a result we get the value of the coefficient | a.

i The specified algorithm is implemented (using the elements NOT 47 and 48, the irepoB 51 and 52 trig, the elements 60-63 of the delay, the elements OR 67, 69-71, the counter 75, the adder 78, the elements} And 92, 95-97, register 99. I The value of the number enters the first .informational input of the accumulator 78: from the register 98 output, the second information input - from the output: multiplexer 38, the modulus value is supplied to the third information input of the adder 78, Receives information from the output of the adder 78.

After the calculation is completed, the modulus, modulo, from the output of the OR 68 pulse is fed to the installation input of the trigger 51, the input of the delay element 60 and through the OR 69 element to the installation input of the trigger 52, as well as to the installation input of the counter 75, resulting in the latter is set to the zero state.

The zero signal from the direct output of the trigger to the input of the trigger 52, confirming the mode of the generator 51 goes to the fourth input of the receiving direction of the adder 78, prohibiting the reception of a number from its fourth information input and allowing it from the first input. A zero signal from the right output of trigger 52 prohibits reception of information from the third information input and allows reception from the second of the adder 78, through the OR 70 element to the input of the delay element 63, through the OR 67 element to the admission input of the adder 78 and the input of the element 61 delays and through the element I 92 to the counting input, counting 75, which counts this pulse. This continues until the result of the operation

of the information input of the adder 78,

on the first, third and fourth control - Q a, / mj-nij. the non-becoming inputs of the operation of which receive a single signal, and the second control input of the operation receive a zero signal.

At this stage, the preparation of the execution of the operation / OBG, / T.; - t, ends. 55 The trigger 51 controls the receipt of information, i.e. either from the output of register 98 or from the output of

Viyitani adder 78, OR or 70 - to the input of the delay element, through the OR input resolution input sum and input of the delay element 61 AND 92 element to the counting input 75, which carries this pulse. So on, as long as the result of the operas

equal to or zero. As a result there will be a negative at the output of the sign, the result of the mat 78 is set to a signal that through the element NOT 47 enters the input of the element allowing passage through the pulse from the output of the element 6 ki, From the output of the element And 97 and

0

five

0 5

0

five

Matrix 78, trigger 52 controls the mode of operation (subtraction or summation), and counter 75 counts the subtraction operations. Starts. First, the operation is as follows.

From the output of the delay element 60, a pulse passes through the OR element 67 to the input of the admission reception of the adder 78, to the input of the delay element 61 and the first input of the element 92, to the second input of which from the inverse output of the trigger 52 in the subtraction mode of the adder 78 receives a single signal. Thus, when performing the operation of subtraction, the write pulse through the element 92 is fed to the counting input of the counter, which counts these pulses.

From the output of the delay element 61, a pulse is applied to the resolution input of the result of the adder 78, the input of the delay element 62 and the setup input of the trigger 51, sets it to one state, prohibiting the reception of information by the adder 78 from the first information input and allowing reception from the fourth.

If the result of the operation / icij -l,. is positive, then the output of the sign of the result of the adder 78 is set to one with ignals, and the output of the equality of the result is a zero signal. At the outputs of element 96 and element 47, zero signals appear. From the output of the element 62 of the delay, the pulse through the elements AND 96 and OR 69 impulse goes to the installation

trigger entry 52, confirming mode

 a, / mj-nij. does not become

viitani of the adder 78, through the OR 70 element - to the input of the delay element 63, through the OR 67 element - to the input of the reception resolution of the adder 78 and the input of the delay element 61, and through the And 92 element to the counting input, counting 75, which counts this pulse. This continues until the result of the operation

negative or equal to zero. As soon as the result becomes negative, then the output of the sign of the result of the adder 78 is set to a zero signal, which through the element NOT 47 enters the input of the element AND 97 allowing the pulse through it from the output of the delay element 62, With the output of the element 97

ta . The order of the analysis of a is similar to the specified order of calculation of a. After the calculation of the coefficient a- is completed, its numerical value is written to the register 99 and the pulse formed by the element OR 71 is fed to the counting input of the counter 74 (adding one to its contents) and to the input

10 elements 56 hold up. If the number at the outputs of the counter 71 (equal to i-1) is not equal to the number at the outputs of the counter 73, then a zero signal is set at the output of the comparison circuit 79, and, accordingly, a single signal vo is at the element output. Thus, a pulse from the output of delay element 56 passes through AND 85 and enters the trigger input for

passes through the element AND 96; 20 calculating the coefficient a; . Wherein

trigger 49 remains in a single state, i.e. adder 76 receives information from register output 99.

This goes on until .25 at the outputs of the counter 73 does not look at the value of the number i-1. In this case, a single signal appears at the output of the comparison circuit 79. The pulse from the output of the element 56 delay through the element

30 and 86 sets the counter 73 to the zero state and arrives at the output of the end of the calculation of block 20, which is a sign of the end of the calculation of the coefficient.

The device (Fig. 1) works as follows.

Element 13 delays the input pulse for a time not less than the total response time of counter 8 and

40 blocks of 15 memory. The memory unit 15 serves to store the values of the modules of the system of residual classes. The delay element 21 delays the input pulse by the time the register 45 is triggered, and the element 22 delays the response time of the register 7. The delay element 26 delays the input pulse pa the operation time in the multiplier 23.

The delay element 28 delays the input pulse by the time of the runout in the adder 32. The power supply element 30 delays the input pulse by the response time of the adder 32. The delay element 35 forms the output pulse with a delay by the counting time of the counter 10. The element 36 delays the input pulse for the time equal to the sum of the response times

enters the setup trigger 52, as a result of which the adder 71 is switched to the summation mode, the passing of the shulses through the AND 92 element is prohibited. Consequently, the counter 75 counts only the pulses, which characterize the subtraction mode. The pulse from element ID 97 through OR element 70 comes through delay element 63, element OR 67 to the receive enable input of adder 78. If the result of the summation is again negative, then the process of summation repeats until the result becomes positive or equal to zero.

If the result is positive, then the impulse is again from the output of delay element 62

 the adder 78 goes into the subtracting mode, through the element 92 and the passage of pulses to the counting input of the counter 75 is allowed.

I

These processes continue.

until at the end of one of the operations of summation or subtraction the result becomes equal to zero. Then, at the output of the equality of the result to zero, the adder 78 establishes a single signal that permits the passage of pulses through the element AND 95 and prohibits their passage through the elements 96 and 97. The pulse from the output of the delay element 62 through the element 95 enters the input of the register record 99 and through the element OR 71 to the first input of the delay element 56 and the counting input of the counter 73. The register 99 records the number from the output of the counter 75, which is the coefficient ag.

The coefficient a- begins to be calculated from the moment it arrives at the input of the .20 (i-1) -th pulse unit. At this point at the input of block 20 there is a number of t-. Coefficient value already

35

Once received, the counter 73 is in the zero state, and at the outputs of multiplexers 37 and 38, information appears with input a, and m, respectively. When a block of 20 (i-1) -th pulse arrives at the input, it is counted by counter 74, at the output of which appears the code of the number i-1, and also this is fed to the input of delay element 53 and the setup input of trigger 49, the process of calculating the coefficient 55

35

1314

counter 8, memory block 15, register 18.

If, on admission to input 4, the device deduction 6i; at the entrance of 12 mouth- | A control pulse is applied, this deduction participates in decoding the code, and in the absence of a control pulse, there is a charge about /; and the corresponding | e-module tp; are not perceived by the device for decoding. At the initial moment, a short pulse arrives at the input 5 of the device, which establishes trigger 3,; cheaters 8, 10, and 11, registers 7, 17,,. .17ts.2, 18, ... .18, J 27 to the zero state, is input to the block jca 20 of the coefficient calculation, and to | Register 19 writes a number with a value of 1. The information input 4 of the device is given the value of the deduction ci,. From the input of 6 clock pulses, the clock pulses of the irits begin to arrive at the input 12.

coinciding with the clock for long-25 15 memory. With the arrival of the first impuls and temporary position.

The presence of a zero signal at the direct output of the trigger 3 prevents the passage of control pulses through element 9, and a single signal at its inverse output permits their passage through element 2. The pulses from the element 2 enter the input of the delay element 22 and the register entry input 7, as a result, the value of the deduction "i, from information input 4 is written to register 7. Since the value of the coefficient a is equal to the value of the deduction oi,, then no further operations are performed on the calculation of a, but the process of calculating the following coefficients begins Comrade;

From the release of register 7, information iiocTynaeT to the first information; the input of the adder 32 and the second information: the input of the coefficient calculation unit 20, to the first information input of which information is fed from the information input 4 of the device.

The pulse delayed by the delay element 22 is fed through the OR element 29 to the input of the reception resolution of the summator 32 and the input of the delay element 28. Since from the trigger 25 to the first input of the receive resolution of the adder 32 a single signal is given, and to: the second and third inputs of the receive resolution of the sum, the ator 32 - a zero signal, after

14

the arrival of a pulse from the output of the delay element 28 to the input of the delay element 30 to the installation input of the trigger 25 and the resolution enable input. The coefficient value appears at the information output of the adder 32 and enters the device output 33 and the information input of the adder 32. Pulse from the output of the delay element 28 It also sets the trigger 25 to the single state, as a result of which a first signal is sent to the first receive enable input of the adder 32, and a single signal to the second and third leads of the receive enable, i.e. adder 32 is ready to receive information arriving at its second and third information. entrances.

Clock pulses from the input of 6 clock pulses of the device are received. on the counting input of the counter 8, the output of which is controlled by the block

A number code corresponding to one appears at the output of counter 8, and the output of block 15 is set to m, and, accordingly, with the i-ro pulse, the value of t is set. From the outputs, memory block 15, information is fed to the information inputs the registers 18,.,. 18 |, and 27. The pulses from the input 12 of the device arrive at the counting input of the counter 11, counting up to K, the Counter 11 performs the counting of these pulses, also coming through the delay element 1 to the installation input of the trigger 3,

0, the first pulse sets it to the unit state, as a result of which they are prevented from passing through the AND 2 element and the remaining pulses are allowed to pass through

5 element and 9.

The output signals of the counter 11 control the operation of the decoder 16, to the gate input of which a pulse arrives, delayed by the delay element 13. When writing to the counter 11 of the first pulse, a single signal appears at the first output of the decoder 16, which arrives at the register recording input 18. When the second control pulse arrives, the single signal is fed to the recording input register-. 182 and so on until the (K-1) -th control pulse arrives. The pulse from the output of the element 13 delay

0

five

also enters the input of the register 27 and the input of the delay element 21, from the output of which it enters the input of the reception permission of the multiplier 24 to the second information input of which is fed a number from the output of the register 19, whose value at the initial moment-time is equal to one, to the first information input the number comes from the output of the register 27. Thus, after the arrival of the first pulse from the input 12, multiplication occurs and the output of the multiplier 24 sets the code of the number equal to

With the arrival of the second pulse from input 2 and the second clock pulse, the code corresponding to the number two is written to the counters 8 and 11, and the value m is written to the registers 18 and 27. The pulse through the element And 9 enters the input element 36 of the delay and the recording entry register 19, and the information from the outputs of the multiplier 24 is recorded in the register 19, i.e.; after the arrival of the second control pulse, the value m in the register 19 is recorded. The same impulse from the output of the AND 9 element, delayed by the delay elements 13 and 21, equal to the response time, the counter 11, the decoder 16 and the register 27, is fed to the input of the reception of the multiplier 24, and since by that time the input of the multiplier If the code of the number t, and at the other input, t, then at the output of the multiplier a number is set equal to t, t, which

the arrival of the third pulse from input 12 is written to register 19.

The second pulse from the output of the element AND 9 is fed to the input of the delay element 36, the output pulse of which is the pulse from which the coefficient calculating unit 20 starts calculating.

The first information input of block 20 receives the values of deductions (rf; from the information input 4 of the device. The second information input of this block from the output of the register 7 is given the value a, to the third information input of the block 20 from the output of the register 17, the value comes a, from the output

and so yes

register

17 meaning

2

but.

Next, respectively, the kth information input of block 20 receives the value a

ki

from the register 17c

k, 1.

t with

ten

15

20

25

thirty

35

40

45

50

55

The (k + 1) -and information input of block 20 is given the value m from the output of register 18, the (k + 2) -th input is the value of m, and so on, respectively, from the output of register 18., to (2k-1 ) -th input enters the value of t :. The modulo value is fed to the 2nd information input: from register 27.

After the termination of the coefficient a. on the information output of block 20, the value a appears, and

, on its control output, an impulse, indicating that the calculation of

coefficient a is complete. Information from the information output of the bioca 20 arrives at the information input of the registers 17, ... 1 7 ,,. and the information input of the multiplier 23, to the other information input of which the value m is fed, from the output of the register 19. The first pulse from the output of the calculation end of the block 20 is fed to the delay element 35 and the counting input of the counter 10, on the outputs of which a value appears. 1, which from the output of the decoder 14 receives a signal at the input of the register record .17, i.e. after the arrival of the first pulse from the output of block 20, the value a from information output 34 of block 20 is written to register 17, after the arrival of the second pulse, from the output of the end of the calculation of the block

20 17 „

the value a is written to the register

,, and so on, respectively, with the arrival of the (k-1) th pulse - into the register of 17 k-o.

The first pulse from the output of the calculation end of the block 20 is also fed to the input of the delay element 26 and the input resolution of the multiplier 23, in which the operation is performed, the result of which goes to its output. The impulse delayed by the delay element 26, through the IL 29 element, arrives at the delay element 28 and the reception enable input of summator 32. By this time, the adder is prepared for summing the numbers supplied to its second and third information inputs.

On the third information input sum-. Mator 32 on the second comes the value of a., and

result a.x m,

output multiplier 23

When a resolution arrives at the input of the result of the adder 32 pulses from the delay element 28 in the code of the adder 32,

The calculated value is a -t-a-iin ,.

With the arrival of the third pulse on the; Device input 12 and the third clock of YOUR pulse on the clock input 6, the counters 8 and 11 record the value 3, and the registers 18, 18, 183 27 correspond to the values of ha

 one

m

g

L-, in register 19 - the value of m, m. For-W | the calculation is made by the block 20 of the coefficient a ,, which is written 17, the multiplier 23 is implied | to the register 11,

| multiplies the values of a, and

.

Then the adder 32 performs the summation and at its output the value is set, is equal to, +,

If, for example, the third pulse has not arrived at I input 12, the third clock pulse is fed to the counting input of counter 8, the output of which has a code corresponding to the diffraction three, then the code corresponding to digit two is recorded in counter 11. From the output of memory block 15, the value of the module in 1 register 18 will not be recorded. With the arrival of the fourth control pulse, the digit code four appears at the output of the counter 8, and the code of the digit three at the outputs of the counter 11. Registers 18 ,, 27 record the value of the modulus. | At the output of the adder 32 sets-with number value

15

20

; a, gp + a t,,

After the arrival of the kth pulse at the device input 12 and the completion of the calculation by the adder 32, a pulse appears at the output of the delay element 30, indicating that the calculation is completed and the final result can be read from the device output 33.

Claims (2)

1. A device for decoding codes represented in the system of residual classes, containing a memory block, an adder, a first counter, two multipliers and two registers, the information input of the device connected to the information input of the first register, the setting input of O which is connected with the installation input into the first counter, with the input set 142932318. 4 -notes of the second register and with the installation input of the device, a clock input of which is connected to the counting input of the first counter, the output of which is connected to the address input of the memory unit, the output of the second register is connected to the input of the first multiplier of the first multiplier, the output of the second multiplier is connected to the information input of the second the registers, the outputs of the first register and the first multiplier are connected respectively to the inputs of the first and second terminals of the adder, the output of which is connected to the input of the third term of the adder with the output of the result of the device, characterized in that, in order to reduce the amount of equipment, it contains a coefficient calculation unit, a decoder decanter, an OR element, a second and a third counter-third register, two groups of registers, two AND elements, two triggers and nine electric the delay elements, wherein the information input of the device and the output of the first register are connected respectively to the first and second information inputs of the block for determining the coefficient, JQ of the first and second groups of information inputs of which are connected respectively to the outputs of the registers of the first and second groups, the output of the third register is connected to the third information input of the coefficient calculation unit and to the input of the first multiplier of the second multiplier, the input of the second multiplier of which is connected to the output of the second register calculating the coefficient is connected to the input of the second multiplier of the first multiplier and with the information inputs of the registers of the first group. one 35 40 45 50 55 with inputs of installation in About registers of the second group, with input of starting the coefficient calculation unit, with inputs of installation in About of second and third counters, with input of installation in About of third register, with installation inputs of About first and second triggers and with installation input of device, input the start of which is connected to the first input of the first element I and through the first delay element from the input r of the installation to 1 of the first trigger, trigger, direct and inverse outputs of the code Topio o are connected respectively to the perms input of the second element AND and with inputs of installation in About registers of the second group, with input of starting the coefficient calculation unit, with inputs of installation in About of second and third counters, with input of installation in About of third register, with installation inputs of About first and second triggers and with installation input of device, input the start of which is connected to the first input of the first element I and through the first delay element from the input r of the installation to 1 of the first trigger, trigger, direct and inverse outputs of the code Topio o are connected respectively to the perms input of the second element AND and With the second input of the first element I, the input of which is connected to the recording enable input of the first register, the device start input is connected to the input of the second delay element, the counting input of the third counter and the second input of the second element I, whose output is connected to the recording enable input of the second register , the output of the second counter is connected to the information input of the first decoder, the outputs of which are connected to the recording resolution enable inputs of the first group, the output of the third counter is connected to the information input of the second A decoder, the outputs of which are connected respectively to the write enable inputs of registers of the second group, whose information inputs are connected to the information input of the third register and connected to the output of the memory unit, the output of the second delay element is connected to the enable input of the second decoder, to the enable input the third register and the third delay element with the input of the resolution of the second multiplier, the output of the first element AND is connected through the fourth delay element to the first input of the OR element, the second input d and the output of which are connected respectively with the output of the fifth delay element and with the inputs of the sixth delay element and enable reception of the adder, the input of which rashesheni is connected to the input of the installation in 1 of the second trigger, to the output of the sixth delay element and through the seventh delay element to the output of the end of the device  unit, the output of the calculation end of the coefficient calculation unit is connected to the input of the fifth delay element, with the resolution input of the first multiplier, with the counting input of the second counter and through the eighth element of the delay with the resolution input of the first decoder, the output of the second element 1i is connected via the ninth delay element to the control input of the coefficient calculation unit, the inverse output of the second trigger is connected to the first control input of the sum of the mattre, the second 5 third input of the receive direction of the second one is connected to the direct and output of the second trigger, inputs i the classical zero and the logical unit i of the device is O 5 0 5 five about five not, respectively, with the first and second inputs of the constant of the coefficient calculation block, 2. A device according to claim 1, characterized in that the coefficient calculation unit comprises two multiplexers, nine NOT elements, a trigger circuit, eleven delay elements, nine OR elements, three counters, two comparison circuits, seventeen And elements, two registers and three adders-subtractors, the first information input of the coefficient calculation unit is connected to the first information input of the first adder-subtractor, the second information input of which is connected to the output of the first multiplexer, whose information inputs to Connected respectively with the second information input and with the information inputs of the first group of the computing power unit of the cofffering unit, the information inputs of the second group of which are connected to the corresponding information inputs of the second multiplexer, the control input of which is combined with the first input multiplexer and connected to the first input multiplexer. the input of the first comparison circuit and with the output of the first counter, the information in the output of the first mat-subtractor is connected to the first information input of the second adder-subtract Ate, the information output of which is connected to the second information input of the second adder-viitatel, with the first input of the second comparison circuit and with the information input of the first register, the output of which is connected to the first information input of the third adder-subtractor, the second information input of which is connected to the output of the second the multiplexer, the third information input of the coefficient calculation unit is connected to the third information inputs of the second and third subtractors and with the second input of the second circuit cf The information input of the third adder-subtractor is connected to the information output of the third adder-subtractor, the output of the second register is connected to the third information input of the first adder-subtractor and is the information output of the coefficient calculation unit, the control input of which is connected to the counting input 2 1429323 a, the input of the first element with the installation of the rigger, the output of the first ki is connected to the first element OR, the output of the scythe input of the resolution of the adder-subtractor delay element pr td pr not ra dy i vh to che ne w hô 15 w ho chi e ne the input of the third delay element, the input of the resolution of the first summator and the input to the first trigger, the inverse output of which is connected to the first input of the receiving direction of the first adder, the second and third inputs of the receiving direction of which are connected respectively to the second the input of the block constant is a factor ent and with the direct output of the first trig 20 element And connected through the fifth Hera, the second input of the constant of the calculator of the coefficient calculation is connected by the first and third control 1 inputs of the first adder-subtractor, with the first and second control inputs of the second adder-subtractor, with the first, third and fourth control inputs of the third adder-second, second control the input of which is dinene with the third control input of the second adder-subtractor, with the second control input of the first adder-subtractor and with the first input of the constant of the coefficient calculation unit, the start input of which is connected to the installation input of the second Pc and the first input of the second OR element, whose output connected to the input of the installation of the first switch, the outputs of the sign and the zero equality of the first adder-subtractor are connected respectively to the input of the first element NOT and the first input of the first element AND, the input and output of the first element NOT connected respectively with the first inputs of the second and third elements And, the second inputs of which are combined and connected to the first input of the fourth element And and the output of the second element NOT, the input of which is connected to the first input of the first element And, the second input of which is connected to the output of the third delay element and with the second input of the fourth element And, the output of which is connected to the input of the installation in О of the second trigger, the inverse output of which is connected to the first input of the direction 22 d receiving the second adder-subtractor, the second and third inputs of the receiving direction of which are combined and connected to the direct output of the second trigger, the OUTPUT of the first comparison circuit is connected via the third element NOT to the first input of the fifth And element, the second input of which is connected to the first input of the sixth And element and with the output of the fourth delay element, out (the first comparison circuit is connected to the second input of the sixth AND element, the output of which is connected to the second input 5 of the second OR element and is the output of the calculation end tim coefficient output of the fifth AND gate connected to a second input of said first OR gate, the output chetver5 0 five ABOUT five 0 the delay element with the first input of the third OR element, the output of which is connected to the reception enable input of the second adder-subtractor and to the input of the sixth delay element, whose input is connected to the input of the seventh; delay element, c. the input of the setup of the second trigger and the input of the resolution of the second adder-subtractor, the outputs of the sign and zero equality of which are connected via the fourth and fifth elements NOT respectively to the first and second inputs of the seventh element AND, the output More than the second comparison circuit is connected to the first input of the eighth And less than the second comparison circuit is connected to the first inputs of the ninth and tenth AND elements, the output is equal to the second comparison circuit. It is connected to the first input of the eleventh element, and the second input is connected with the output of the seventh delay element and with the second inputs of the eighth and ninth elements AND, the third inputs are combined and connected to the output of the second element AND, the code of the fourth element OR is connected to the first input of the twelfth element AND, the output of which is connected to the counting input of the third .a counter, the output and the input of the installation in Oh which are connected respectively to the information input of the second register and the output of the fifth OR element, the first and second inputs of which are connected respectively to the outputs of the ninth and thirteenth elements ntov And, exit seventh element, And connected to the second input of the tenth element And, the output of which is connected to the first input of the thirteenth element AND and through the sixth element is NOT to the first input of the fourfold element And, the second input of which is combined with the second input of the thirteenth element And and connected to the second input of the eighth element And, the output of which is connected to the third input of the tenth element AND, and to the second input of the third element OR, the third input of which is connected to the output of the fourteenth element AND, the third and fourth inputs of which are connected respectively to The output of the third element And through the seventh element is NOT with the first input of the eleventh element AND, the output of the fifth element OR is connected to the input of the recording resolution of the first register, with the installation input to About the third trigger, with the first input of the sixth element OR and through the eighth delay element with the first the input of the fourth element 25 true trigger is connected to the second that OR, the output of which is connected to the enable input of the third adder-subtractor and through the ninth delay element with the input of the tenth delay element, with the enable input of the third adder-subtractor and with the installation input of the 1st third trigger, the inverse output of which is connected to the first the input direction of the third adder-subtractor, the second, third and fourth inputs of the reception direction of which are connected respectively to the inverse and direct outputs of the fourth trigger, with the direct output of the third trigger This OR, the output of the eleventh element AND is connected to the third inputs of the eighth and ninth elements OR, the code of the ninth element OR is connected to the installation input of the second Pere, the outputs of the sign and zero equality of the third adder are connected respectively to the eighth element and the first input of the fifteenth element I, the second input of the KOTOPO-i45 gistr. It is connected to the output of the tenth delay element and to the first inputs of the sixteenth and seventeenth elements And, the second inputs of which are combined and connected to the output of the ninth element NOT, whose input is connected to the first output of the fifteenth element And, the input and output of the eighth element They are NOT connected respectively to the three inputs of the sixteenth and seventeenth elements AND, the output of the sixteenth element AND is connected to the second input of the sixth element OR and to the first input of the seventh element OR, the second input of which is connected to the output of the seventeenth element And and to the input of the installation in the 1st fourth trigger, the installation input in Oh of which connected to the output of the sixth element OR, the output of the seventh element OR is connected via the eleventh delay element to the second input of the fourth element OR, the inverse output to the fourth input of the twelfth element AND, the output of the fifteenth element AND connected to the resolution enable input of the second register and the first input of the eighth 0 element SH the output of which is connected to the counting input of the first meter and to the input of the fourth delay element, the code of the second counter is connected to the second input of the first comparison circuit, the output of the first element AND is connected with the second input of the eighth element OR, and with the first input of the ninth element OR, the second input of which is connected to the first input of the second ele5  . ) flP AND g g.