SU1429062A1 - Synchronism indicator - Google Patents

Abstract

The invention can be used in control systems to control frequency synchronism and to improve the accuracy of determining the state of synchronism. The synchronism indicator contains a phase discriminator 1 consisting of AND 8, Y elements, inverters 10, 11, and element OR 12, time converter 2 is the code, two-threshold comparison unit (DBS) 3, analyzer 4 is state synchronous, state of elements AND-NOT 18-20, triggers 21, 22, counters 23, 24, decoders 25, 26 elements AND 27 and element OR 28, display unit 5, element OR 6 and element And 7. If synchronism is present, the frequency of the infodmation is one and the reference signals entering the phase discriminator 1, db. equal and shifted by 90, In phase discriminator 1, counter 15 counts the number of pulses, respectively. phase mismatch. The code for this number is compared in DBL 3 with the specified max, possible phase mismatch. With a phase shift falling into a predetermined range, the DBL 3 generates a logical 1 signal sent to the analyzer 4. To prevent a false trigger of the sync indicator. chronism analysis of the magnitude of the phase mismatch is carried out in a certain time interval. 2 nl. /)

Description

Chshg.} I 1-

The invention relates to automation and can be used in control systems i to control frequency synchronism.

The purpose of the invention is to improve the accuracy of determining the state of synchronism,

1- FIG. Figure 1 shows the structural electrical diagram of the indicator of synchronism; in fig. 2 - timing charts of the device.

The synchronism indicator contains a phase discriminator 1, a time converter 2 — a code, a two-threshold comparison unit 3, a synchronism state analyzer 4, an indication unit 5, an OR 6 element, and an AND 7 element.

The phase discriminator 1 contains the first and second elements AND 8 and 9, the first and second inverters 10 and 11 and the element OR 12. The time converter 2 time - the code contains the generator 13 clock pulses element AND NOT 14 and the counter 15. Two-threshold block 3 of the comparison contains a threshold shaping circuit 16 and a comparison circuit 17.

The synchronization analyzer 4 contains the first, second and third elements AND- NOT 18-20, the first and second triggers 21 and 22, the first and second counters 23 and 24, the first and second decoders 25 and 26, the element AND 27 the element OR 28.

Synchronization indicator works in the best way.

Information and reference signals f and fg (.fig. 2a, b) are fed to the corresponding inputs of the first element And 8, as well as to the corresponding inputs of the element ШШ; 12 phase discriminator-torus 1. If synchronism is present, the frequencies fy and fg are equal and shifted to PP. At the output of the first element And 8 of the phase discriminator, pulses are formed (fig.2b), which arrive at the first input of the element II of the 14 E converter 2. At the second input of the element EH 14, the clock pulses from the generator 13 of the converter 2 (FIG .2g). Selected pulses (fig. 2e) are sent to the counting input of the NAND 14 element to the counting input of the counter 15, which reads the number of pulses and stores it until the voltage on the installation input of the output element OR12 of the phase bottom of the criminator arrives - tirovanny the second inverter 11

g

five

0 5

0

Q s Q.

five

(figg). In this case, the counter 15 is set to the state O, and the binary code of the number of pulses from the output of the counter 15 is supplied to the comparison circuit 17 of the two-threshold comparison block 3, to which two threshold values in the binary code are supplied from the threshold shaping circuit 16. The maximum number of counting pulses is reached when the phase is shifted from one of the signals relative to the central position by +90, the minimum - by the shift / ge phase by -90. In accordance with the predetermined maximum possible phase mismatch, the lower and upper thresholds are set in the diagram 16 for forming the thresholds 5 which are fed to the comparison circuit 17.

When the phase shifts of the input signals that fall within the specified thresholds range, the comparison circuit 17 generates the voltage of the logical unit, which is fed to the information input of the trigger 21 of the analyzer 4 and is rewritten to its output (Fig.2l) by the generator 13 clock output from the element And 1 (FIG. 2k) and selected by the second, AND 9 (FIG. 2) through the gate from the first inverter 10 (FIG. 2e) and on the And 7 element of the OR 6 element (FIG. 2n. The beginning of the pulse of the OR element 6 gate is formed first impulse counting in counter 15 transform 2, the end of the strobe coincides with the beginning of the setting pulse from the output, the second inverter 11 (Fig. 2). If there is no read pulse at the trigger output 21, the voltage corresponding to the input at the time of the last read pulse is remembered at the forward output of this trigger. The logical unit of the trigger 21 is fed to the first input of the Third Element IS-NOT 20.

In order to prevent the synchronism indicator from false triggering and to improve the determination of the synchronism state, the synchronism indicator provides for analyzing the magnitude of the phase mismatch over a certain time interval during which the comparison circuit makes decisions about finding the phase shift within the set range. For this, from the direct output of the trigger 21 of the analyzer 4, the voltage of the logical unit is supplied to the second input

the second element AND-NOT 19, the first input of which receives a signal from the second inverter 11 (figl-). At the output of this element IS-NOT 1U, pulses are formed (fig.2AVj carrying information about the device being in the tolerance of phase mismatches. The pulse sequence arrives at the counting input of the first counter 23 of the analyzer 4. After accumulating in the counter 23 a predetermined number of pulses determined by the decoder 25, A voltage is generated at the output of the decoder 25. This switches the second flip-flop 22 to the state corresponding to the logical unit at its output, and a signal is received from the AND-NE element 20 to the input of the display unit 5.

If the phase relationships between the input signals are violated, the counter 23 is reset by supplying

The synchronism indicator, containing a series-connected phase discriminator, a synchronism state analyzer and an indication unit, is distinguished by the fact that, in order to improve the accuracy of determining the synchronism state, a time-code converter, a two-threshold comparison unit, the OR element and the And element are entered, the first input which is connected to the output of the OR element, the inputs of which are combined with the inputs of the two-threshold comparison unit and connected to the signal outputs of the time converter - code, signal input and clock

to the installation inputs of the counter 23 and trigger 22 of the signal from the output of the descrambler 25 whose output is connected to the corresponding number 26 of the counter pulses by twisting the output and input of the phase disperser 24. The installation signals are generated when a predetermined number of pulses arrive at the counting input of the second counter 24 and the triggering of the decoder 26.

The reset of the counter 24 is carried out either by pulses from the inverter 11, selected on the element AND 27, which arrive at the first input of the 35

the criminator, the output of which is additionally connected to the setup input of the time-code converter, the output of the two-threshold comparison unit is connected to the first control input of the synchronization state analyzer, the second control input of which is connected to the output of the And element, the second input of which is connected to the gating 35

or 28 or the voltage to the logical output of the phase discriminator.

unit arriving at the second input of the element OR 28 from the direct output of the trigger 21. The output pulse of the element OR 28 zeroes the counter 24.

Claims (1)

Invention Formula Synchronization indicator containing phase-connected phase discriminator, synchronism state analyzer and display unit, characterized in that, in order to improve the accuracy of determining the synchronism state, a time-to-code converter, a two-threshold comparison unit, an OR element and the And input element are introduced connected to the output of the OR element, the inputs of which are combined with the inputs of the two-threshold comparison unit and connected to the signal outputs of the time converter — code, signal input and clock the output of which is connected to the corresponding output and output of the phase dis- the output of which is connected to the corresponding output and output of the phase dis- the criminator, the output of which is additionally connected to the setup input of the time-code converter, the output of the two-threshold comparison unit is connected to the first control input of the synchronization state analyzer, the second control input of which is connected to the output of the And element, the second input of which is connected to the gate output of the phase discriminator. . I Lj  L li and to P .2 AND illlilllllllllllimilimilllllHIIII Jl Jl