SU1425872A1 - Video signal interpolation device - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to improve the accuracy of interpolation. The device contains serial code to parallel converter I, switches (K) 2 and 6, delay blocks 3-5, 7 and 8, comparators 10, code converter 11, computing unit 12 levels of interpolated samples and frequency doubler 13. The doubler 13 generates switching pulses having a doubled frequency in comparison with the received signal. These pulses arrive at K 2 and 6. In this case, K 2 compresses the received sequence of samples with zero-level samples, which will later be replaced by interpolated values. As a result, in a digital signal at output K 2, each received sample will be interspersed with zero level samples. In K 6, the zero-level samples corresponding to the intersected samples corresponding to the sifted through the coding process are replaced. As a result, and at the output of K 6, a reconstructed sequence of alternating received and interpolated samples is formed. The goal is achieved by introducing K 2 and 6 and doubler 13. Dana il. Completions BV 12. 3 Il. ъм (Л с:

Description

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The invention relates to a television technique and can be used to interpolate a video signal in systems with element-to-element transmission,

The purpose of the invention is to improve the accuracy of interpolation.

Figure 1 shows an electrical block diagram of a video signal interpolation device; FIG. 2 -: block diagram of the calculation of the levels of interpolated samples; FIG. 3 shows diagrams illustrating the work.

The video signal interpolation device contains a converter I of a sequential code into a parallel one, the first switch 2, the second 3, the first 4 and the third 5 delay blocks, the second switch 6, the fourth 7 and fifth 8 delay blocks, the comparator block 9 consisting of of the ten comparators 10-1-10-10, the code converter 11, the block 12 for calculating the levels of interpolated samples, the doubler 13 of the pulse frequency,.

The block 12 for calculating the levels of interpolated samples (FIG. 2) contains the first 14, second 15 and third 16 adders, first 17, second 18 and third 19 logical addition blocks, ten keys 20-29, six multipliers 30-35, first 36 and second 37 inverters.

The device operates as follows.

The interpolation algorithms (FIG. 3) are as follows. In the process of efficient coding based on the through-element transmission of samples, the original orthogonal raster structure (FIG. 3) is converted into a chess structure (FIG. 3b). As a result, when restoring the original The structures on the receiving side can be used to interpolate any sample scanned during the coding of the information on the level of four samples (A, B, C, and D, Fig. 3b) forming the nearest environment of the restored reference. In addition, in a sequential reconstruction procedure, the following level data were also used to solve the interpolation problems: x nearest samples (E and F, FIG. 3b) recovered in the previous line interval. During the logical interpolation process, the most likely samples are assigned to the recoverable samples. values determined by

We estimate the differences in the levels of the samples of the nearest environment. For this purpose, the absolute values of ten differences (i 1.10) between the levels of all six of the above samples of the nearest environment are calculated. The magnitudes of these differences are then compared with the threshold cff ,,. ,, determined by the level of noise and texture components in the transmitted image. As a result of this comparison, ten binary analysis variables are formed:

G1 at L; i

X; i 1,10

lo with D: cG „p.

Then, using analysis variables, control operators are formed y, corresponding to different (in general, k) variants of the interpolation algorithm.

The device has 12 interpolation algorithms, which are combined into three groups according to the belonging of the interpolated reference to the most characteristic structural elements of images, and one smoothing algorithm.

The first four interpolation algorithms correspond to the cases when three samples of the four basic (A, B, C, and P) were the closest surroundings of the recovered reference, with the same.

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 0.25A + 0.5B + b, 25Cpri y, x, x x x j

S.J2 0.25B + 0.5G + 0.25Dnpkyi, zs ,,;

Sjj - 0.25C + 0.5D + 0.25A for yj - XjXjXjX x x;

Sj, 0.250 + 0.5A-Yu, 25Vri y, x, x, x, x, x, Xj,

However, since all the subsequent algorithms use all ten analysis variables xj, t, e, for the formation of control operators y, additional information obtained by using auxiliary samples of Ey F is taken into account, it is necessary to clarify the record of control operators with considering all ten variables xj:

y, - x,;

for xj x x x x j x x x xj x / g;

UZ 5 - Xj X J

These algorithms are used in the case of. when the interpolation count belongs to the contours oriented in the horizontal or in the vertical direction.

The second group of algorithms corresponds to the cases of interpolated samples belonging to extended single-element strokes of arbitrary orientation. To detect them, it is necessary to use information about the levels of auxiliary samples E and F recovered in the interval of the preceding line:.

 0.5 (B + D) with yj.- X, x.jiejX, Xyi4x i, X, x,;

sjt- 0.5 (A + C) at Y4- x, XjiCjX4XjX x, XgXyX;

 F at. Y7- x ,, x ,, x, X, x,;

S, E with% - x, XjXjX ,, XgX, x.

The signal at the output of the first switch 2, each received sample, is interleaved with zero samples. Such a conversion allows for all subsequent elements to use the same clock source, which is the doubler 13.

10 The output signal of the first switch 2 is fed to the inputs of the second block 3 delays per line and at the same time the inputs of the first block 4 delays, where the delay 15 of the sequence arriving at its inputs takes place for two clock intervals.

The algorithm corresponds to belonging. At its outputs, signals are generated to carry an interpolated reference to D, corresponding to a temporal position of a vertically oriented single interpolated sample Sj. screwdriver (fig.Zv). Second output signal; algorithms Sjjr and - to the slope of the block 3 delay, it arrives at the single-element strokes. the third block 5 of the delay and simultaneously the group of algorithms used for the first information inputs is used to interpolate the contours, orientally the second switch 6. The third block 5, which are orientated in the diagonal delay directions, provides a delay of three sequences for its inputs interval. With his

Sj9 0.5 (C + D) with y - X | XjX x Xj.X (X, x, J5jX; outputs corresponding to the delay by Sjiff 0.5 (A + B) with Ys-xs XjX x XjXyX, x Qda; Q one clock interval, iSisSiS.: T-St; x; | x -; ::: x; x :: p- signals A, and from the output signals corresponding to 1 clock

 . interval, - sampling signals C.

In all other cases, i. in the second switch 6, none of the control operators is the replacement of samples; the zero level is one (to 1.12) ,. n, corresponding to the smoothing coding process, interpolated by the coding process, interpolated by Sj, i3 0.25 (A + B + C + D). samples arriving at the second Reviewed algo- rity of the switch

interpolation rhythms are realized by barely 6 from the outputs of block 12 for calculating the level in the following way. more than interpolated samples. Switching pulses go to the inverted digital signal to the successive input of the second switchboard, the coded code, the distributor 1, where the serial frequencies generated by the doubler 13

code is converted to parallel, is-45 pulses. As a result, the elements used in all functional functions of the second switch 6 are formed at the output. The output signal is the reconstructed sequence of the receiver, 1 is fed to the information-alternating received and interpolating inputs of the first switch 2, of twisted samples. Therefore, the outputs in the second compaction of the conventional switch 6 are at the same time a sequence of samples of the outgoing outputs of the device by zero-level interpolation blocks, which are video signals.

the interpol- o signal of the second commuted value will be replaced later. For this purpose, pa 6 also arrives at the inputs of the quadruple of its control input from the output of the ud-gg of the delay block 7 per line and the divider 13 commutes more to the inputs of the fifth delay block 8, the pulses having doubled as compared the delay to the position with the received signal is the frequency of the sequence received at its input. As a result, in digital samples there are three clock intervals.

From its outputs corresponding to a delay of one clock interval, samples of signals E are removed, from outputs corresponding to a delay of clock intervals — samples of signals Bj and outputs corresponding to a delay of three clock intervals — samples of signals F. I Thus With the help of the second 3 (and the fourth 7 delay blocks on the loop of the first 4, third 5 and n - toro 8 delay blocks, at any jth time point, a set of 4x six samples of the nearest environment used in the process of restoring the data samples on the skeleton logical interpol algorithms - | cues. The formed samples A, B, C, D, fe and F are then fed to the inputs of compilers | 10-1-10-10-10. With their help, ten absolute values of differences i are formed (fig. 3d), which After a comparison with a threshold of / 5 on you- (during each of the comparators, ten binary binary code signals corresponding to the analysis variables XL are formed. The output signals of the comparators 10-1 g-10-10 arrive at the address inputs of the converter 11, made in the form of a permanent storage device, the outputs of which are formed code combinations of control signals of block 12, corresponding to control operators y.

. The code combinations of the signals, the controls, proceed further to the control input of the block 12, calculating the 1–2 levels of the interpolating samples, the information inputs of which receive the signals of the samples A, B, C, D, E and F. Under the influence of the control signals for each The recovered sample Sj is implemented by one of the 13 interpolation algorithms considered. Restored counts from the output of block 12 are sent to the WTO | 1e informational inputs com {utatora 6 and further to the output of the video signal interpolation device

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Claims (1)

Invention Formula A video signal interpolation device containing a serial to parallel converter, the input of which is an information input of a video signal interpolation device, a first delay unit, connected in series a second delay unit, the input of which is combined with the input of a first delay unit, and a third delay unit connected in series and fifth delay blocks, a series of comparators connected in series, a code converter and a block for calculating the levels of interpolated samples, the second in One of which is connected to the output of the first delay block, the third and fourth inputs are connected respectively to the first and second outputs of the third delay block, and the fifth, sixth and seventh inputs are connected to the first, second and third outputs of the fifth delay block, respectively, the first, The second and third outputs of the fifth delay block are connected to the corresponding inputs of the comparators block, differing in that, in order to increase the interpolation accuracy, a pulse frequency doubler is input, the input of which is the input frequency This device interpolates the video signal, as well as the first and second switches, the control inputs of which are connected to the output of the doubled pulse frequency, while the signal perzyho switch is connected to the output of the serial to parallel converter, and the output is connected to the input of the second delay unit, the first and second the signal inputs of the second switch are connected respectively to the output of the second delay unit and to the output of the block for calculating the levels of interpolated samples, and the output is connected to the input of the fourth block and delay. 0 nineteen  Jk F % 25 About About About About oh oh oh oh oh oh oh VIA- “I a | b-11 , L, -1b-C1 - | {-A | if IS-F L, -1C-P | ev.3