JPH029281A - Picture coder - Google Patents

Abstract

PURPOSE:To suppress the distortion of a video image to be sent caused due to a code error in a transmission line by splitting one frame of a picture into plural blocks depending on the arranged position of a picture element, applying coding in each block and detecting the code error for each block at the reception side. CONSTITUTION:The arrangement of the picture element in a frame is converted from a digitized video signal in a picture element arrangement conversion circuit T4 and the picture signal transferred from the circuit T4 by each block is subject to subtraction with a preceding frame data of the relevant block at a subtraction circuit T5. A difference signal obtained by the subtraction circuit T5 is coded by a coding circuit T11 and an error detection code is added by an error detection code addition circuit T12 in the unit of blocks and transferred to a frame combining circuit T13. Thus, a video image distortion generated by the occurrence of the transmission error is dispersed in the frame and suppressed considerably by reducing the time required for error recovery.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to an image encoding device that employs image encoding that is resistant to transmission path errors.

(2) Conventional technology When transmitting video encoded data using the digital transmission method, code errors may occur within the transmission path. When applying a video encoding method that encodes frame 1, the open lid signal, if a code error occurs during transmission, the content of the frame memory on the receiving side will match that of transmission 01)1. Code errors will continue to occur in subsequent decoded signals. As a means to recover from this 21 inch error,
There is a method of transmitting an intra-frame encoded signal from the transmitting side at a fixed period (periodical refresh), or a method of sending a refresh request signal to the transmitting side by detecting a code error on the receiving side.
Based on this, a method (demand refresh) is used in which an intra-frame encoded signal is sent from the transmitting side.

When the conventional refresh method is applied, when a code error is detected, the receiver (S side) has no choice but to replace the current frame with the previous frame when reproducing two images.

Furthermore, until the mismatch in the contents of the frame memories between the transmitting side and the receiving side is recovered, that is, the demand reflexon-L signal is
・Monthly) I Freno due to default, internal signal reception port E
4(ro) for not being properly replayed for a long time.

demand [In the refresh method, when an error occurs, 1
It is necessary to transmit 7 digits 1)'l++3 within the frame for the screen, and the amount of tl1m to be transmitted increases. In addition, by dividing the frame into several regions and performing code error detection on the receiving side in each region, intraframe encoding No. 111 for code -1'1 recovery should be transmitted. Limiting the area to a small size and efficiently refreshing the area requires 11. It is possible to shorten the interval between 'i', but the distortion of the image subject will be applied to the area where the sign ≤ 1'' (distortion occurs). Target 7. Movement compensation (31 in the hole,
In the video coding system that aims to improve efficiency, 2) If a code error occurs in a certain area, and motion compensation prediction is performed in another area that includes part of the data in that area. There is a possibility that this motion compensator /l1ll contains the code 21 "1", and there is a problem that the decoding error will be transmitted to other areas.

As described above, in a high-efficiency video encoding system based on encoding an inter-frame difference signal, the conventional code error recovery method has had major problems.

(3) Purpose of the Invention The present invention relates to a high efficiency video encoding system based on frame-to-frame encoding. In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to suppress distortion of transmitted video caused by code errors on a transmission path, and to reduce the amount of information that needs to be transmitted when an error occurs.

(4) Structure of the invention (4-1) Differences between characteristics of the invention and conventional technology The present invention consists of 1
By dividing one frame of an image into multiple blocks according to the pixel placement position, encoding each block, and detecting the code and X-shape for each block on the receiving side,
The content of the frame memory on the transmitting/receiving side when a code error occurs - the content of the frame memory necessary for failure, including the 7'T code - is reduced, and the location where video distortion occurs is divided into two areas.
Furthermore, while image distortion is occurring, the main feature is that it is possible to eliminate the image distortion by interpolating the error occurring pixel with neighboring pixels.
This is significantly different from the conventional technique, which performs code 3-cycle recovery by refreshing a single frame.

(4-2) Example An example in which the number of blocks I'J is set to 4 is shown below.

FIGS. 1 and 2 are block diagrams that do not show the configuration of an embodiment of a transmitter and a receiver (11) of the present invention, respectively.

TI is image input G:hi child, 'r2 is AD conversion circuit, T
3 is the same 1υ1 (No. 3 separation circuit, T4 is the image>H arrangement conversion circuit 5T, 5 is the subtraction circuit, 'l'6 is the switch circuit, 'r
7 is an adder circuit, TO, T9 is a changeover switch circuit, T'l
Oa-d is a frame memory, T11 is a code Σ conversion circuit TI
2 is an error detection code addition circuit, T13 is a frame assembly circuit, T14 is a transmission circuit, T15 is a data output terminal, T16
is a data input terminal, and T17 is a demand refresh receiver (
3 circuits, T18 is a control circuit.

Further, R1 is a data input terminal, R2 is a receiving circuit, R3 is a frame separation circuit, R4 is a decoding circuit, R5 is an addition circuit,
R6 is a switch circuit, R7 and R8 are changeover switch circuits,
R9a to d are frame memories, RIOa to d are code error detection circuits, R11 is a pixel arrangement inverse conversion circuit, R12 is a pixel interpolation circuit, 1113 is a DA conversion circuit, R14 is an image output terminal, R15 is a control circuit, and R16 is a beam frame. Assembly circuit.

R17 is a transmitting circuit, and R18 is a data output terminal.

FIG. 3 is a diagram for explaining a method of pixel arrangement conversion, and FIG. 4 is a diagram for explaining a method of pixel interpolation. In FIG. 4, 1 is a pixel to be interpolated; 2. 3. 4 is an adjacent pixel, 5 is a previous line pixel group, and 6 is a current line pixel group.

The transmitter and receiver shown in Figures 1 and 2 (3 parts are shown below) will be renovated.

(No. 11 is input from terminal T1, synchronization t, A x separation times: tyr 3, horizontal and vertical inter-directional signals are 811 minutes: after that, in ΔD change 1fi circuit T2, Analog (1) is converted into a data digital signal (S). At this time, the switching/sampling clock is connected to the same signal (i'JI i3'E) separated by the synchronizing signal distribution circuit T3.
＋It will be hooked. Also, this same amount (the number is "all?") is notified and the control circuit T18 can identify the frame of the signal currently being processed. (For the east signal, the pixel arrangement of the frame memo is changed by 1 in the 2-pixel arrangement conversion circuit T4. A element arrangement is changed.) The method of mulberry is shown in FIG.

The diagram on the left side of FIG. 3 shows the arrangement of pixels on the screen for one frame in which the number of pixels in the I line is 2M and the line size is 2 N 111.1. Change the pixel arrangement of this pixel group using the following method. First, as shown in Fig. 3, the lines are numbered from 1 to 1 from the top and represented by y, and the pixel numbers on 1 line and 2 are also numbered in the same way and represented by 1 variable X. If each pixel is represented by a grid point (x, y), and the coordinate system before transformation is P (x, y) and the coordinate system after transformation is P'(x',y'), Figure 3 shows The transformation shown is of order one.

P (x, y) l P'(m, n) : (x
, y) = (2m-1, 211-1), then r'(x, y
) l P'(M+m, n): (x, y
)-(2m, 2n-1) then P(x, y) l
P'(m, N+n): (x, y)=(2a+-1
, 2n) then P(x, y) l-i'(M+m
, N+n): (X, y)・(2m, 2n) However, when 1m-1 is an integer from M, and n-1 is an integer from N! i! A block constructed by such pixel arrangement conversion is shown on the right side of FIG. Each of these blocks is MXN
It consists of lattice points.

The block-by-block video data generated in this way is sent out one after another in time series for each block by the pixel arrangement conversion circuit T4, and the sending timing is notified to the control circuit 01 (I8). The control fffD circuit Ti1l is connected to the I, lJ switch circuit T8. T9 is switched to select one frame memory board 10a-d corresponding to each block. For example, if block 1 corresponds to frame memo J i''loa, 1
The frame memory for each frame is reduced to iB. The image signal data of the corresponding block of the previous frame J is stored in the frame memory FIOa, and the image signal transferred from T4 for each block I'J is transferred to the 8 corresponding blocks in the castle circuit T5. U 7ri no Moe Fray 1. A total of three differential signals with respect to A' are generated.

However, the switch recess; 1δT6 is normally in a conductive state.

The difference signal obtained in this way is added to the image signal of the previous frame J in the adder circuit 'F7, and 'F+'j
The data is stored in the frame memory of the Ni Zrobe II.

Further, the differential signal that is not illuminated by the computation circuit T5 is encoded by the code output uFr T11, and further by the error detection code addition circuit '12, a C4 detection code is added at the 11th position, and the error detection code is added to the frame 1. , ■11 is transferred to section 1'l3.

Following block 1, the next block is circuit T4.
The same operation is repeated one after another.

The frame assembling circuit TI3 waits for one frame worth of blocks to be transferred, and constructs a transmission frame together with error detection codes for each frame.

In this way, the i:t signal is sent to the transmitting circuit '1'14.
is transferred to the demand refresh signal TI7 and transmitted to the receiving side through the data output terminal T15. The block number is notified, and the information is further notified to the control circuit T18. Upon receiving this 1ffl information, the control circuit T18 disconnects the switch circuit T6 and controls the encoding so that the encoding becomes intraframe encoding. .

No. 48 obtained from the data input terminal RI is received, ζI
It is received at I+11'I'8R2. This received signal is
Frame molecule i11 separated into blocks by circuit R3 2
The signals are sequentially transferred to the decoding circuit R4. At this time, the block number 41' that is being transferred? The information is sent to the control ta11 circuit R15. Control circuit RI5 controls changeover switch circuits R7 and R8 based on this block number information.
IR the frame that corresponds to the block number that was previously assigned to the river. The decoding circuit R4 performs decoding on a block-by-block basis.

Here, it is assumed that sol l: l, ri 1 have been processed, frame j, menu ri 9a are missing 4 in ji 1 fuku.
I will explain it as a variety of things. The signal 4 obtained as a result of the decoding in R4 is added to the signal of the corresponding Zoroku in the previous frame, which is input to frame 1°, in the adding circuit R5. Placement inversion circuit R1
Sent to 1. Here, Suisou y-circuit R6i;1.
1lli to J73 Xi! When it is notified from the decoder 4 that it has received an intra-frame quality synchronization signal from the transmitting side, it enters the 1jJi state.

Following block 1, the primary blocks are transferred one after another from circuit R3 and processed in the same manner. The decoded signal of block IIi obtained in this way is 1
In the pixel layout inverse conversion circuit R11, the transmission side pixel layout conversion circuit T4 performs a conversion that is inverse to the conversion described above. That is, the pixel group arranged as shown in the right diagram of FIG. 3 is converted to the arrangement shown in the left diagram.

In addition, the frame memories R9a-d are each 7T No. 31.
It is accompanied by error detection circuits RIOa-d, and code errors for each block detected here are notified to the control circuit R15 along with the block number information. Upon receiving this notification, the control circuit R15 controls the refresh request circuit R1.
(+), and the block number (I') is sent to the data output terminal r21.
It is transmitted to the sending side through B. Pixel arrangement inverse conversion circuit R
The image signal of l frame unit obtained from 11 is 2 pixels t
Interpolation processing for nine pixels is performed in the inter-ili circuit R12. That is, the block number information in which the code error has occurred is interpolated using five adjacent pixels for the pixel corresponding to the block notified from the it;II 1211 circuit R15. 11 (An example of the 1-interval method is shown in FIG.
Interpolation is performed by a weighted average of pixel 4 at the back of the screen and pixels 2 and 3 of the front line pixel group 5. This interpolation process is
This process continues until the code error in the corresponding block LJ7 is recovered.

If no code error occurs, no 9-pixel interpolation is performed. The image (No. 3) subjected to interpolation processing in this way is digitalized (35
1 image output O: 1;
Output to child Rl 4.

In addition, in the explanation given in 1-, the pixel arrangement is changed by the 1 pixel arrangement conversion circuit T4 and the pixel arrangement inverse conversion circuit R11 (Kuwa describes the method of dividing into 4 blocks, but the method of dividing by 1 block []
7. Therefore, it can be easily achieved that G) can be any integer other than 4.

Furthermore, in the transmitter shown in FIG. 1, when the demand refresh signal is received in the circuit F17, the control circuit T18 switches to intra-frame encoding. For the block 1 and block 1ijii pixels that have occurred without control, interpolation processing is performed using adjacent pixels. By transmitting the information along with the information indicating the frame, the receiver (11) can recover the code error while continuing decoding with interframe encoding.

(5) Effects of the Invention As explained above, according to the present invention, transmission errors occur due to transmission error 4I: in real-time video transmission that is highly efficiently encoded using interframe difference signals. This method has the advantage of reducing the time required for error recovery by dispersing the video distortion that occurs within the frame, and further suppressing the code error to a greater extent each time pixels with code errors are interpolated with surrounding data.

Furthermore, even when a coding system that performs 5vJ multiplied by complement a1 is applied, according to the present invention, (2) the problem of code error propagation described in the prior art section is solved.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of the sending section 3 of the present invention, and FIG. 2 is a diagram for explaining an embodiment of the receiving section of the present invention. FIG. 3 is a diagram for explaining a method of pixel arrangement conversion, and FIG. 4 is a diagram for explaining a method of pixel interpolation. T I =-both input': lj -'I'-'T'
2...AD A li circuit, rj3...Dohoshin 5J
Dividing circuit 2 'r4... Pixel arrangement change I isolation circuit. '1'5...Remaining times bly,]゛6...Switch 4h
“Kun T7/Additional 19 circuit, 1” 8, 'I'
9-... Cut IQ Suy 'J-circuit, 'T'lO1]
~d...Fre J4 mechiri, ``I' l 1...
・Coding circuit i"l 2...Error detection cylinder ・Si addition circuit il', %-1' 13...Fileno, A, 11 circuit, i-14...Sending same product, T l 5・
... Data output terminal completed -1i" l G... Data input 0:1; Child, 'l' 17... Demand reflex reception circuit, T18... ljl '+111 circuit Rl...
Data manual terminal, [N2...Receiver 11' skin 1-3)
L・-ノ, minute 1 sweet circuit, 174... decoding circuit, 12
5 adder circuit, R (i...S inochi times i13. l
'? 7, R8・Cut (good sui y 'f-concave i?r
l R'1 to a (1...Frei 1.! Shiri 212
1 On -d -717:j ,:,"i detected amount &
fi, RI l...pixel arrangement inverse conversion circuit,
RI2...Pixel interpolation time Y! ), RI3...I) conversion circuit, RI4... Image output O:1: completed, R15/control circuit, I? I (i...refrenonomy request circuit, [n1
7... Sending (3 circuits, RI8... data output terminal, ■
...Pixel interpolation target pixel, 2, 3.4...Adjacent pixel used for interpolation, 5...■Line pixel group, 6...
Current line pixel group. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] (1) The transmitter divides the input image signal into multiple blocks by rearranging the pixel arrangement within one frame using a predetermined method, and encodes the interframe difference signal for each block using a predetermined algorithm. means for adding a code for detecting code errors in the image signal for each block on the receiving side; and means for intra-frame encoding the signal corresponding to the designated block based on a request from the receiving side. The receiving side has a means for decoding the received image data block by block using a predetermined algorithm, and a means for synthesizing an image signal by rearranging the arrangement of pixels from the plurality of blocks. Means for detecting code errors in data for each block and notifying the transmitting side along with information specifying the block in which the code error has occurred, and interpolating the pixels corresponding to the block in which the received code error has been detected using adjacent pixels. An image encoding device comprising: means for outputting an image. (2) When encoding a specified block based on a request from the receiving side as described in claim (1) above, based on the request from the receiving side, the block in which a coding error has occurred is transmitted. A means for encoding an inter-frame difference signal with information interpolated with adjacent pixels on the side and notifying it together with the encoded information to the receiving side, and a means for decoding the inter-frame difference signal with the frame interpolated with adjacent pixels on the receiving side. An image encoding device characterized by having means for.