SU1506554A1 - Video signal coder - Google Patents

Abstract

The invention relates to computing and imaging technology. Its use in systems (for example, satellite) of digital transmission of television signals improves the accuracy of the encoder. The encoder performs a fast Hadamard transform for four consecutive samples of a digital video signal and adaptive coding of the obtained transformant elements. At the same time, by choosing the value of the second element depending on the values of the remaining elements, its quantization interval is smaller than in the prototype, due to which an increase in coding accuracy is achieved. 2 Il.

Description

The invention relates to computing and imaging technology and can be used in digital television signal transmission systems, for example, in satellite systems.

The purpose of the invention is to improve the accuracy of the encoder.

FIG. 1 shows a functional diagram of the video signal encoder in FIG. 2 - time delay block.

The video encoder contains a block of 1 time delays, the first - the fourth summation blocks 2-5, the first - the eighth subtraction block 6-13, the inverting block 14, the code comparison block 15, the first - fourth switches 16-19, the first sixth blocks 20-25 the divisions, the first and second blocks 26 and 27 of calculating the number module, the parallel code converter 28 to the serial code and the synchronization block 29. FIG. 1, informational inputs 30 and inputs 31 of a reference code are designated.

The time delay unit 1 can be executed (FIG. 2) on the shift register 32 and the buffer register 33.

FIG. 2 denotes a clock input 34, a synchronization input 35, and the first to fourth outputs 36-39.

Modules calculating blocks 26 and 27 can be implemented on programmable modules. converting additional difference code into

about

Od 01

SP

413

3150655А

my code, if the difference arriving at the EEPROM is negative.

The video signal in digital form (sampled and quantized at 6A level) is fed to the inputs of the time delay unit. In block 1 of the time delays, four consecutive samples are applied to the input.

about

H

a and

a.j video signal into a parallel four-element signal. A group of four image elements undergoes a rapid Hadamard transformation, and as a result, elements of the Hadamard transform are formed:

bo a „+ a ,,,

L ,, - 1-a, -a ,, ,,;

.,.

Elements b and b,

are formed at the outputs of the third and fourth blocks 4 and 5 summation, and the elements b and b - at the outputs of the third and fourth blocks 8 and 9 subtraction.

Since O 6 a; 63 (i 0,1,2,3) then from (1) it follows that O: b (, i 252, a - 126 bj 126, where j 1,2,3.

Thus, it is necessary to spend 8 bits on encoding b. Moreover, one of the 8 bits b is significant. The video data stream flipping by 1.5 times in the considered encoder was obtained by seven-bit encoding bd and three-bit coding b rt, b a rt a. . but

L, b, b ,. If on chetfe

six-digit elements a, a, a, a, a. In total, 2A bits are allocated, then 1 bit is necessary to spend on the elements of the transformants b, b, b and b. 24/16 1.5 times less.

On the receiving side, the elements a, of the decoded group are restored according to the rule:

 (Bn + b, + b, + b,);

1 l l a l

T (b, -b, + b, -b,))

A) l

ar h-lh-ts);

A IA A L

  d (b „-b ,,).

where b; - Elegants transformants after coarsening.

five

The six transmitted bits b are the higher bits of the eight-bit code bj. One of the three transmitted bits b is sign. The other two bits are calculated by an adaptive procedure.

Adaptation is the selection of the transmitted value bj (h 2,3)

depending on the b value for

about

each coded quartet of elements a, a, a, a and a. The adaptive coding is based on the dependence of the boundaries (upper and lower) of the change in L (j 1,2,3) on

jbj if bo 6,126 | bj J (232-b,) if bo 126 (2)

0

five

five

0

five

0

five

0

An adaptation of b is the choice of the transmitted value of C, depending on the values of bg, b and b, for each coded group. The value of b is selected at the following intervals:

-bo-t- | b, + b, (6 b, (, l. with bo 126

or

-252 + bn + | b - b, ib, b252-b, - - | bh + b, | (3)

at 126 1 C 252.

The video encoder works as follows.

A video signal in digital form, sampled and quantized at 64 levels, is input to the input 30 of block 1 of time delays. In block 1, a coded group of 4 elements is formed: a, a, a. Moreover, the first outputs (Fig. 2) enters a, to the second - a, to the third - a 2, and to the fourth - a ,. At the outputs of the first and second blocks 2 and 3, the summations are formed () and (,). At the outputs of blocks 6 and 7 of the subtraction, the differences () and () are formed. On the output of block 4, the first element of transform bd is formed; at the output of block 8, the second element b, at the output of block 5, the element b – j, and at the output of block 9, the element of transformant b. In block 15, a code comparison is made to compare the value L of each coded group with the reference code of the number 126 received at the inputs 31 of block 15. If the signal

at the output of block 15 is equal to 1. In block 14, the code of the element b is inverted and the code of the number (255-lp) arrives at the outputs of block 14, since with six-bit coded elements and the code b ,, is eight-bit. In expression (2) | bJM3Kcl (252-bn), if b, 126. For the sake of simplicity, instead of calculating the difference (252-bd), the computation (255-bp) is implemented by simply inverting b, which does not lead to an erroneous recovery of the elements transformants. The control input of the switch 16 receives a signal from the output of the block 15 of the comparison of codes, the information inputs - the signals b and b, i.e. (255-bd). If the controlled signal is 1, the output of block 16 is connected to b 255 - bd. In dividing unit 20, dividing b (or bd) is made by 4. The result of dividing C is fed to the inputs of a divider of dividing units 21 and 22. In block 21

calculating the limits of b, as functions of bp, bj and b ,. The upper limit ei of change b is equal to

cx

 bo-lb -b, | b, -2 | a, -a,)

J252-b, | “252-b -2 | a„ -a, |

at O b „126,

at bd 1 26.

For each group is calculated

15

prio bd

at 126 - Ü 252

The value of | (e, | / 2 is determined by dividing block 24, and the value of / 2 by using block 25

division is done. module 25 is divided. At subtraction unit 10, b is received at C and the sign b is assigned to the quotient from division. Thus, in blocks 21 and 22, on inputs b and b, there are blocks for calculating modules and | bj | . Three-digit private code

B without two least significant bits (i.e. divided by 4) from the output of block 4 and | a, -a, 1/2. As a result, b is determined, l

1 bj from division (one bit d - zn30

 . Other meaning

Ckb

(for bo 126) is calculated using subtractor 12, the input of which receives the inverse value b also without 2 least significant bits. Both values are transferred to the converter.

28. For example, if L 70 and L 54,

then C 70/4 17 and bi bj /

/ C 3. Code b, equal to 011 (per- "" arrive at the switch 17,

The first bit is a sign). At reception, 35 p, is controlled by a signal from the output of block 15 comparison codes. If this signal is 1 (i.e., b,; 126), the outputs of switch 17 connect the transform element to the output of block 12 on the subtracted side, according to the rule:

Similarly calculated

Di

Bo 4

| 3, -ai |

M.-1 ..

252-bo la, -a, |

b C 3 -17 51.

B is calculated in the same way. neither

In blocks 26 and 27 of the module calculation, | a, -aj and (I, respectively) are formed. The necessity of calculating these modules explains e5 the following calculations:

Ibj-b | | ag + a, -a2-a, -ao + a,, / 2 | a, and | bj-bb, | 2).

Thus, to calculate Ib b, | and (Expression 3) there is no need for an additional subtractor and adder, since the values of (a, -Y}) and (aQ-aj) are determined using blocks 7 and 6 of the subtraction, respectively. go to the inputs of switch 19, which

The fifth and sixth blocks 24 and 25 are divided by the most significant (sign) differences, from the fifth to the eighth blocks 10–13 subtraction and from the second to the fourth switches 17–19 are intended for

50

at O bo r 126; at 126. with b 252.

&

One of two values of up from the output of switch 17 and one of two values of Ls from the output of switch 18 by postures b,. If b, O, then the outputs of block 19 connects to the Ld. In block 23, b is divided by L

25 At block 10 subtraction arrives

B without two least significant bits (i.e. divided by 4) from the output of block 4 and | a, -a, 1/2. As a result, b is determined, l

thirty

 . Other meaning

Ckb

(for bo 126) is calculated using subtractor 12, the input of which receives the inverse value b also without 2 least significant bits. Both values are passed to switch 17,

Similarly calculated

Bo 4

| 3, -ai |

M.-1 ..

252-bo la, -a, |

go to the inputs of switch 19, which

at O bo r 126; at 126. with b 252.

&

One of two values of up from the output of switch 17 and one of two values of Lc from the output of switch 18 is post-controlled by higher (sign) values

p dam b,. If b, O, then the outputs of block 19 connects to the Ld. In block 23, b is divided by L

or

L „and

The three bit code "ib" is transmitted to the parallel code to serial converter 28, at the output of which, for each coded block, a sixteen bit code word is formed from each four six bit elements, i.e. 1.5 times the flow is compressed. The same compression is achieved using a known encoder. In the proposed encoder, the accuracy of rtpeo6-video signal enhancement is enhanced by using a more efficient quantization strategy. B. , b, / C 1. in the prototype: b, b / CJ O and on the receiving side the value of b is equal to 0. In this encoder, for b -5 "c O, the value (b |) is calculated to be 10. Then C , 10/4 2, and finally Lb b, / C, 2. On the receiving side, the reconstructed

-

equals 4, which is more accurate than

value

in a known coder.

To clarify this, let us consider the extent to which

to vary the least.

From (1) it follows that

in the above b, b, b, b.

20 20 20 20

10 5 10 S 10

;

+ 10 s o

70 50 10 30

ABOUT

ABOUT

Oh b

Oh b

- 10 30

The joint solution of these inequalities gives the following change interval by: 45

- 10 b,

thirty.

Substituted b, bj and b in (3), the same change interval b

get (: 50

- 40 (20 + 10) bbi 40 - (20 - -10), since L 126, - 10 b, BSO.

Those. The decoding (3) is valid for any coded group.

From expression (3) with (2) it can be seen that the interval of change of b, depending on

B

less than the interval, from only b.

3

hanging

five

to

15

20

25

thirty

35

40

in: 45

m 50

-.

. 55

-

Consequently, when going to the quantization scale b, depending on b, b and bj, the quantization interval decreases by

Claims (1)

wL I b, t-bj | b ,, + b, | . In the proposed encoder for quantization b, as many binary units are allocated as in the known encoder, but due to the fact that the quantization interval b is smaller than in the known encoder, the coding accuracy increases. As a result, during restoration, the image quality of oblique contours and texture plots is improved at the same flow compression ratio. Invention Formula A video encoder containing a time delay block whose information inputs are encoder information inputs, the first to fourth summation blocks, the first to fourth subtraction blocks, the first to fourth division blocks, the inverting unit, the first switch, parallel code converter, serial the synchronization unit and the code comparison unit, the first inputs of which are the inputs of the encoder reference code, the first output of the synchronization unit is connected to the synchronization inputs of the parallel-converter converter In the sequential and time delay block, the first and second outputs of which are connected to the first inputs of the first and second summation and subtraction blocks, respectively, the third and fourth outputs of the time delay block are connected to the second inputs of the first and second summation and subtraction blocks, respectively, the outputs of the first and second the summation units are connected respectively to the first and second inputs of the third memory and subtraction blocks, the outputs of the first and second subtraction blocks are connected respectively to the first and second and inputs of the fourth summation and subtraction units, the outputs of the third subtraction unit are connected to the inputs of the divisible fourth division block, whose outputs are connected to the first information inputs of the parallel code to serial converter, the outputs of the third summation unit are connected to the second inputs of the code comparison unit, inverter block inputs first information entry  1506 the first switch and the second information inputs of the parallel code to serial converter, the outputs of the fourth subtraction and summation blocks are connected to the inputs of the third and second split blocks, respectively, whose outputs are connected to the third and fourth information inputs of the parallel code to serial converter, inverter block outputs and the code comparison unit is connected respectively to the second information and control inputs of the first switch, the outputs of which are connected The inputs to the inputs of the first division unit, the outputs of which are connected to the inputs of the second and third division dividers, the second and third outputs of the synchronization unit are connected to the clock inputs of the time delay unit and the parallel code to serial converter, the outputs of which are encoder outputs. characterized in that, in order to improve the encoder accuracy, the second - the fourth switches, the fifth - the eighth subtraction blocks, the fifth and sixth division blocks, and the first and second blocks are entered into it; 5A 0 five 0 ten neither the number of modules whose inputs are connected to the outputs of the second and first subtraction blocks, respectively, the first inputs of the fifth and sixth and first inputs of the seventh and eighth subtraction blocks, respectively, are combined and connected to the outputs of the third summation block and the inversion block; the numbers are connected to the inputs of the fifth and sixth division blocks, respectively, the outputs of which are connected to the second inputs of the fifth, seventh and sixth, eighth subtraction blocks, respectively, whose outputs connected, respectively, to the first and second information inputs of the second and first and second information inputs of the third switch, the control inputs of which are combined and connected to the output of the code comparison unit; the outputs of the second and third switches are connected respectively to the first and second information inputs of the fourth switch, control inputs and the outputs of which are connected respectively to the outputs of the third subtraction unit and the inputs of the divider of the fourth division unit. 2