SU1425698A2 - Device for interfacing digital computer with analog objects - Google Patents

Abstract

The device relates to computing technology and can be used as a device for interfacing digital and analog computing computers, as well as for connecting a digital computer with an object. The aim of the invention is to expand the functionality by automatically finding the tolerance zone of the tested DAC and A / D converters by changing the set of test patterns. The device contains a DAC group, an ADC group, five switches, two analog switches, an address decoder, an address counter, a polling cycle decoder , sequential approximation register, start-stop generator, buffer register, tolerance control unit, three elements OR, group of elements AND –NE, group of elements AND, 2 Il. SL

Description

N

The invention relates to computer technology S can be used as a device for interfacing a digital and analog computer, as well as for connecting a digital computer to an object and is an improvement of the invention according to the author. № 1130856 „

The aim of the invention is to expand the functionality by automatically searching for the zone of tolerance of the penetration of the CCL and the ADC by changing the set of test: combinations

Fig with 1 shows a block diagram of the device; Fig 2 is a block diagram of the tolerance control unit.

The device contains (FIG. 1) the third switch 1, the first switch 2, the permanently memorized block 3, the group 4 digital-to-analog converters (DAC), the fifth switch 5, the counter 6 of the address, the decoder 7 of the polling, the first 8 and the second 9 analog switches, a group of 10 analog-to-digital converters (ADC) decoder 11 addresses, second 12 and fourth 13 to which start-stop generator 14 buffer register 15, the first element lUli 16, register 17 successive approximation, the third element OR 18 j group of elements AND NOT 19- 22, a group of elements And the second 23-27f lement rsi 28.

The permanent storage unit 3 contains (FIG. 2) the first 29 and second 30 counters, the first element of the ISHL 31, the first trigger 32, the third element AND 33, the element 1SR-NOT 34, the mode register 35, the second element OR 36; the first element is 37, the sixth element is 38, the setup zone setup register 39, multiplexer 40, the group of rto-standing storage nodes 41-44, the second element 45s comparison node 46, the cycle number register 47, the fourth 48 and n 49 elements And, the second trigger 50, element 51, delay, register 52 display “

Switch 1 is for dl. switching information from commu- nator 2, either from output buses, or from block 3 “Information from co-shooter 2 goes to group 4 of the DAL“ Communi-

o

0

five

0

five

0

five

The first analog switch 8 transmits information from the DAC of converters of 4 groups to the analog output of the ShAVyh in operating mode, or transmits information through the first analog inputs of the second analog switch 9 to the ADC of group 10. The second inputs of the second analog switch 9 for transmitting the input analog information in the operating mode, the INPUT of the switch 5 is connected to the input of the switch 2, the inputs of the address decoder 11 and the switch

The output of the mode setting (P) of unit 3 controls the transmission of information and is connected to the control inputs of switches 1, 13, analog switches 8 and 9, and a generator 14, the output of which is connected to the input of counter 6 of address. respectively, with the Shvv input bus and the buffer register 15o. The outputs of the addressable ADC from the ADC group 10 are connected to the information inputs of the IZ switch, and its outputs are connected to the information inputs 1 "wto shtotapopa 13 ,. The latching outputs of the coding end of the addressed A1Sh groups of the ADC 10 are connected to the first element OR 16, the output of which is the bus of the QC coding end and connected to the corresponding input of the block 3 and the input of the buffer register 15, the outputs of the address decoder 11 are connected to the control inputs of the slot DCH 4 and n-DIT ADC groups of the 1C ADC group, and the output with address Ap is also connected to the input of the logic condition (Ap) of unit 3. The output of de1frarator 7 of the end of the polling cycle is connected to the input of the register 17 successive approximations, which is connected to o noimennmi input unit 3 and the counter 6 addresses. The first K outputs of the buffer register 15 are connected to the input of the OR element 18. The output of the VilEi 18 element is connected to the input of the first AND 19 element of the group, the second input of which is connected to the zero output (to - (- 1) th of the buffer register 15 "Single output (k +) - th bit of the buffer register 15 is connected to the first input

The tator 5 controls the transfer of the inforn - 55 house of the second element AND-NOT 20 of the group 1 of the SECH of the switch 2 and connected to the bus and the second input is connected to the address ShA, the output of the counter 6 with the ad-zero output (q2) of the second bit bead and decoder 7 polling cycle. Fern register 15. Single output

(K + 2) -th bit of the buffer register 15 is connected to the first input of the third element AND-NOT 21 groups. The second input of the third element of the IS-NE 21 group is connected to zero output (k + 3) of the first buffer register 15. The output (nl) -ro of the buffer register 15 is connected to the first input of the last element of the IS-NOT 22 group, the second the input of which is connected to the zero output of the buffer register 15 The outputs of the elements AND-NOT 19-22 groups are connected to the first inputs of elements AND 23-26 of the group whose second inputs are connected to (n-1) output of the register 17 successive approximations and to the group of address inputs block 3. The output of the n-th bit of the buffer register 15 is connected with the first input of the element AND 27 of the group, and its second input is connected to the n output of the register 17 of sequential approximation and the same input of the address group, the inputs of block 3. The outputs of the And 23-27 elements are connected to the inputs of the I-UIH 28 element. The output of the OR element 28 is connected with input Malfunction (SN) of unit 3 of tolerance control.

The device works as follows.

The potential on the bus for setting the device mode determines the mode of operation of the multi-channel interface device, which happens to be working and monitoring. Moreover, the control mode is subdivided into the submode of checking the absence of catastrophic failures and the submode of tolerance control. In operating mode, the output potential of P block 3 is equal to one. In this case, the data output bus is routed through switch 1 to switch 2 input, the cable to data cable Schwv through switch 13 connects to switch 12, address bus through switch 5 connects to address inputs of switches 2, 12 and address decoder 11 address, start stop the generator 14 does not work, the contacts of the first and second analog switches B and 9 are in the normally closed state and the outputs of n-bit D / A 4 groups are directly connected to the output analog buses of the AC device, and the information inputs -disable ADC 10 sub coding

0

five

0

five

0

five

0

five

0

five

Groups are not directly connected to the input analog busbars ShAvh.

Information output through the device is carried out via the output bus Shviv through switch 1, switch 2 and the n-bit DAC group 4. The address of a given digital-to-analog conversion channel is carried out via the address bus of the AC, by the signals of which switch 2 connects the output bus Shviv to the input the corresponding n-bit D / A converter, and the number code is written to the D / A register by the strobe signal of the address decoder 11. Further, the information in analog form through the normally closed contacts of the first analog switch 8 is fed to the analog output buses of the SHAVs.

Information is entered through the device via the Shvv input bus via switches 13 and 12 and n-bit ADCs 10 of the bit-coded group. The address of the specified analog-to-digital conversion channel is carried out via the bus address bus, according to the signals of which the switch 12 connects the input bus Shvv device to the output of the corresponding n-bit ADC bit coding. Signal The start of coding to the corresponding 1st ADC 10 of the group comes from the address decoder 11 radially. The signal End of coding to the same bus QC is received from the corresponding output of the addressed ADC via the element OR 16 after the coding process is completed. Signal presence The end of the encoding indicates that the data on the output bus is ready. Analog information is fed to the inputs of n-bit ADCs of bit-coded coding from the input analog busbars ShAVh through the normally closed contacts of the second analog switch of bodies 9.

Thus, in the operating mode, the interface device operates by the corresponding addressing of the conversion channel. At the same time, the information is output synchronously with the addressing, and input after the arrival of a signal. End of the coding from the previously addressed A / D conversion channel. In this case, the digital-to-analog conversion path also consists of P channels.

In the control mode, the signal potential on the mode setting bus (output P of the element And 37 of block 3) switches the switches 1, 5, 13 of the first and second analog switches 8 and 9 and starts the start-stop generator 14 о. 1 is connected to the output of multiplexer 40 of block 3, the output of switch 1 is connected via switch 13 to. input buffer register IS. the address inputs of the switches 2 j, 12 and the input of the address decoder 11 are connected via the commentator 5 to the output of the counter 6 of address 5, the first and second analog switches 12 or & 9 disconnects the p-bit DAC outputs 4 groups from the output analog outputs of the inputs of the p-outputs x AC 11 10 of the group-wide encoding from the input analog buses of ShAVh and switch the output of each of the CDL 4 groups to the corresponding input of P АЩЩ1 10 Groups, With the help of P-polar analog switches 8 and 9, you create a measurement. a circuit allowing the test signal from the corresponding DSL 4 group to be fed to the input of each ADC 10 group,

Thus, in the control mode, the device is disconnected from the external circuits, the output channels are closed to the input channels, and the cannuses are addressed from the output address counter and the start-up generator in cyclic mode from the start-stop generator 14-. The input and output data registers are, respectively, output on the multiplexer 40 bus of the tolerance control unit 3 and the buffer register 15. The information entered from the output bus of the multiplexer 40 is ree; the commutators 1 and 2 into addressable 1 | AP 4 groups are converted into analog form, then goes to the input of the corresponding ADC group 10 through the first and second analog switches 8 and 9, where it is converted back to digital form by a command from the address decoder 11 addresses and through switches 12 and 13 is entered into the buffer register 15, NPA on this verification scheme allows vshvl be faulty nodes in the digital portion of the input-output channel and analog C via elements 17-27 are carried out the detection and localization of sudden failure.

The main volume of the device equipment is ADC and DAC. Therefore

The detection and localization system. The sudden failure mode is oriented to take a turn to troubleshoot the transducer nodes. For

devices having normalized

The metrological characteristics, which are the ADC and CGS, are separated by sudden failures, resulting in a simple failure of the device, and gradual, the presence of which can be detected only by metrological verification. The first type of failure characterizes the reliability of the device in the usual sense, the second - kat

the ecological reliability of the measuring means.

The operation of the detection and localization system, sudden failures, is based on the fact that the physical implementation of n-bit and n-bit ADCs of bit-wise coding provides for the nalgchi B of each of these identical sets of standards, x measures and logical operators. To implement an n-bit DAC, a set of standards is needed, the weights of which are arranged according to the binary law, and a set of keys that are important for them is the role of binary coefficients oi;

Similarly, for physical 0

In order to implement an n-bit ADC of bitwise coding, a set of z 3 and n standards 3 of whose weights are arranged according to the binary law and n switches, is implemented,; binary coefficients oi; In case of failure of any of the nodes that implement in the structure of the DAC and A1SC the function of the standard of the coefficient of; or logic control devices, a gross failure of the device will occur, equivalent to the failure of the entire device.

Assuming the equal ranges of the output signal of the n-bit DAC and the input n - bit AID of a bit-coded coding, the connection of the ADC input to the SchS output allows you to verify the absence of sudden node failures. If in the structure of the DAC to create the output signal V, a standard with a weight of 2 is connected to the adder and the nominal value of this standard is met by the requirements of metrological consistency5

/one

then, to compensate for the input signal V in the structure of the ADC of the bit-coded coding, it is also necessary to connect a standard with a weight of 2 to the subtractive node, which will be reflected in the output code of the ATP. The sudden failure of the node that implements the standard, or a key element that implements the coefficient S; , both in the DAC and in the ADC, will cause a discrepancy between the input and output codes of the test circuit.

The order of detection and localization of sudden failures is as follows. If for tolerance zone converters

sinfulness is equal to the input of the DAC code

± ti, then, by submitting

N, 000 ... 10.

.00

J

TO

in which only the k-th bit has a single value, and the input code N satisfies the condition

Von

 . . w

l i

2n + q

where q is fiVon

- low bit weight for a serviceable DAC and ADC,

at the output of the latter, the following limit code combinations are possible: N ,, 000 ... 1111 ... 1 - when adding errors of converters with a positive sign, N, 2 000 ... 00. „01 - when adding errors of converters with a negative sign.

Combining k lower-order bits into a group with equivalent weight

Q 2

if a

necessary in the event that

1 / Aq.

In the case of use of precision transducers as part of an input-output device, the k value is 1. For converters with an error of up to 0.25q, or in the presence of a high noise level in the connecting circuits, a group of lower k bits discernible against the background noise is necessary to consider as a single bit with a weight of Q.

N

0

eight

The analysis of the code combinations N ,, and, 2 allows us to draw the following conclusions: if at least 1 unit in the output I bits of the output code of the ADC appeared, then we can assume that the reference weight Q is healthy and it turned on, i.e. The oi key is also valid when working on power; if (k + 1) the bit of the output code of the ADC is O, then the key is oi-Ki. not included permanently; other values of these bits at the output of the ADC can be considered as faulty, indicating the presence of

sudden bounce.

Thus, the test code combination N allows you to test for the absence of a sudden failure of the standard with an equivalent weight Q, the correct operation of the odo keys to turn on and the key of-lu + i) to turn off both in the DAC and in the ADP combined in the test scheme. Moreover, for the purpose of analysis, there is no need to compare the entire code combination N with the output code A1D1, but it is enough to check the presence of a unit at least in one of the lower bits of the output code and the presence of a zero in (k + 1) th digit .

The following test code combination may be

N 000

..01011 ... 1

35

TO

As in the previous case, after applying the double conversion error at the ADC output, it is possible to obtain the following two extreme deviations of code combinations:

45

N

2 (

000 ... 0100 ... About

TO

N

21

 000 ... 0110 ... 0

to

It is possible to analyze the codes N ,, and N / j ,,, but to notice that in the absence of sudden failures and when the metrological characteristics of the nodes are within the normal range, the unit in (to + 1) -th bit is saved, and in (to 2) -m bye can not.

Therefore, if output, the code combination N j is in the range between the N and N. codes, it can be argued that the standard with weight Q (k-vi) is valid both in the ADC and in the DAC, the key elements of the chi dm) work correctly for (they were checked for shutdown before the test code), and the key elements of cil (KiZ) work properly for shutdown,

To derive the above statements, it suffices if there is a priori information about the test results with the test code N, and about how to conduct the test with the test code Nj, analyze the bits for and (k + 1) of the output code of the ADC. If (k + 1) -and bit is equal to one, and (k + 2) -th is zero, then there are no sudden failures of the nodes tested at this stage. All other values of the indicated bits of the N 2 code combination are indicative of sudden failure.

The following test code combination may be

N,

00, .. 010011 ... 1

After the position of the double conversion error at the output of the ADC: it is possible to obtain the following two extreme deviations of code combinations:

Nj, 00 ... 01000 ... O,;

TO

Njj 00, .. 01010 ... Oj

TO

From the analysis of N, and Njj it follows

that in the absence of sudden failures, the discharge (k + 2) is always equal to one, and the discharge (k + 3) is always zero. Checking the status of bits

(k + 2) and (k + 3) of the output code of the ADC

there is a monitoring of the health of the discharge standard (k + 2), the correct operation of the keys o (and + 2) for switching on (they have already been checked for shutdown) and the correct operation of the oC keys (k + u on

shutdown.

Similarly, in the test code combination, the value of the low order bits is saved as in N or

N,, moving the unit in the remaining (nk) bits in series in N4 - (k + 3) -th bit, in Nj - (k + 4) -th

bit, etc., is monitored for the absence of sudden failures of the D / A nodes up to the bit number (n-1). The sign bit is checked only for inclusion, since

its malfunction in the off position would not be possible for the operation of the D / A converter and the A / D converters to be valid when checking the previous bits.

In the control mode signals on

The initial setting bus of the WELL will reset the address counter 6 and the register 17 successive approximations. At the same time, the zero code on the output bus of the 6 ajjpeca counter addresses the first DAC of group 4, and the outputs of register 17 of successive approximations address the first code word in ROM 14. It should be noted that register 17 of successive approximations functions similarly to chip 155 IR17, but on output buses the unit moves sequentially, the ROM 41 is a static type ROM, equipped with

output register. However, due to the specific features of the device, it uses only a cell with addresses

000.,. 001 000 ... 010 000 ,,. 100 001 ... 000

100 .., 000

The first test code combination, qi N, from the output of the ROM 41 through switch 1 and addressed from the output of the counter 6, the channel of the switch 2 is fed to the input of the first DAC 4 group. Addressed from the output of the same counter 6 through the decoder 11 addresses, respectively, the same DAC on the strobe signal from the decoder 11 writes the test code N into its register and converts it into an analog signal that is fed to the input of the first ADC 10 of the group. After a certain delay, set by the so-called frequency of the start-stop generator 14, which is necessary to establish an analog signal at the output of the DLC with a given accuracy of 5, the count 6 of the address is one and the address on its output bus changes.

In this device, all digital-to-analog conversion channels have even addresses, and analog-1 digital conversion channels are odd. The counting of the first unit in the address counter 6 leads to the launch of the first ADC 10 of the group by the trigger signal through the address decoder 11. At the same time, the output of the encoding ADC through the addressable channel of the switch 12 and, the switch 13 is connected to the input of the buffer register 15. Upon completion of the encoding process by the signal. The end of the encoding through the P input element OR 16 is converted to the buffer register 15,

The prerequisite is

T,

 ;

where T |. - start-stop period of the generator 15;

T - ADC coding time. Thus, the result of the double conversion of the test code N is entered into the buffer register 15. This checks the first k and (k + 1) -th bits of the first converters 4 and 10 in groups. Indeed, if there are at least one unit in the first to the bit, and the zero is in the (k + 1) bit, then at the input of the AND-NOT 19 element are all units, and at its output O. In this case, the output of the element And 23 will also be zero, despite the fact that it is unlocked at the first input from register 17 of successive approximations. Zero at the output of the element And 23 corresponds to zero on the bus fault (output n-to-input element OR 28). If there is no one on the first outputs of the buffer register 15, or the inverse () output is zero, which indicates a failure in the verifiable Dai or A / D converter, then at the output of the AND –NE 19 element the unit that goes through the element AND 23 and

42569812

element OR 28 per fault bus. The occurrence of a unit at the output of the element OR 28 indicates the presence of a failure.

When the next unit is numbered in the counter 6 of the address, the next address is set at its output. Now addressing the second

10 DACs of the 4th group, in which the code from the first ROM 41 is entered in the same way as the described sequence. When the next unit is stored, the code addressing the second

) 5 ADC 10 groups, the result of encoding which is similar to that described by the pro-. the process for the first ASH1 group is entered into the buffer register 15. The received code combination is used with the element 20 and 23-27, the elements OR 18, 28 and the elements AND-NOT 19-22 of the group is checked for missing. Next, a third group 4 DAC, and then a third group 10 A / D converter, etc. are addressed.

25 Thus, all DACs 4 and A / D converters of 10 groups are tested in pairs with a test code N. The last address that forms the counter 6 is the address (2P-1). With

30, the arrival of the next pulse counter 6 is reset, i.e. the zero address is formed again, and the decoder 7 of the polling cycle generates a pulse, which is fed to the input of the register 17 of successive approximations, as a result of which the unit potential moves from the first output of the register 17 of successive approximations to the second. In this case, the second group element 24 is unblocked, and the output of the first ROM 41 establishes the following test code combination N, the process of entering the code Nj into the digital-to-analog converter, group 4, read the double conversion results from the group's ADC 10, and write the result of the conversion to buffer register 15 the behavior is the same as for code N. However, the result of double conversion must necessarily contain a unit in (k-4-1) -th bit and zero in (k + 2) -m bit. The fulfillment of this condition is verified by the second element AND-NOT 20 of the group and the second element AND 24 of the group. The result of the test is determined by the state of the output of the IChi 28 element. After checking all pairs of DAC 4 and A / D converters of 10 groups in pairs for the test code Nj. produces again35

45

50

55

13

with resetting the counter of 6 address and Shch. The next unit in the register 17 consecutive approximations. This leads to the start of a new verification cycle with the code pattern Nj, which is read from the first ROM 41.

Checking the output code combination is carried out similarly with the help of the third elements IS-NOT 21 and I 25 o. After checking all and the ADC of the last code combination: the process can continue with the code for the new cycle, since the register 17 successive approximations works on a cyclic principle, The transient from the control mode is drying with a change in the potential on the device.

Thus, by controlling the output state of the element OR 28, one can determine whether there are catastrophic failures in the structure of the DAC and the lil.

In this case, the fault is determined with an accuracy of the number of the mircd in the pair of transducers, which are currently the address

Consider the second submode of the control mode; the submode of tolerance control, in which the operation of unit 3 was introduced.

Unit 3 includes ROMs for storing a set of test combinations that are turned on by TSA1T and ADC of the device along a ring circuit. Each of ROM A2-44 contains its own set of test codes, which are chosen in such a way that from ROM 41 to ROM 44, the zone of tolerances of turnable devices expands. The operation of the entire control mechanism of block 3 is constructed so that, first, for test verification, codes from a ROM with a narrow tolerance field are used, for error; if in the controlled ADC and DAC of the device an error is detected greater than that given by this set of test combinations, then the actual tolerance zone of the scanned devices is determined automatically. Since addressing is a combination of

when checking with any test kit

the output codes are of the same type,

then in this device the problem is solved by a set of a series of ROMs addressed simultaneously, the outputs of which are switched by multiplexer 40, which selects the ROM currently operating.

Initially, the trigger 32 is set to B a single state by the signal on the NU bus, and the trigger 50 through the OR 31 element is set to zero. Then, from the output of the trigger 32, the formation of a single potential on the P – Pe20 bus at the output of the element And 37 is resolved. The single potential on the bus P means the control mode and the signal on this bus reconfigures the measuring circuits of the entire device and allows the generator 14 to work (Fig. 1). The appearance of a cool potential at the output of the trigger 32 will block the element I 37 and, on its start, regardless of the register 35, there will always be a zero potential that

2Q that puts the entire device into working mode, and the control mode stops for "

Next, the device operates as follows. At zero address in the counter 29, the verification of the DAC and ADC of the device starts from the ROM with a set of test combinations with the narrowest tolerance zone, if the tolerance zone is not npOH3Oiimo for any of the devices being tested, then on the fault bus leaving the EJHi 28 element, the signal is not on the whits. The calibration cycle on this test code sequence can be repeated.

multiple times as specified by register 5

35

47 numbers, cycles (for example, a set of buttons). This is necessary to confirm the static reliability of errors on a given tolerance zone. If no fault is detected, then trigger

The transition to verification by another set 50 will remain so and will remain in the zero state of the test combinations, with a wider tolerance for possible error, which is stored in another ROM, d, Since the tolerance zone is defined. Then, upon completion of a specified number of calibration cycles on a given code sequence by a signal from comparison node 46, through the element

A set of test combinations, ME-49, is reset / set to zero trigger;

when moving from ROM to ROM, it is within this discreteness, that is, within the accuracy of this discrete

P

4256981А

is determined by the actual tolerance zone of the rotating devices. Since the addressing of a code combination when checking with any set of dough

the output codes are of the same type,

then, in this device, the problem is solved by dialing from a series of ROMs addressed simultaneously, the outputs of which are switched by multiplexer 40, which selects the ROM currently operating.

Initially, the trigger 32 is set to B a single state by the signal on the NU bus, and the trigger 50 through the OR 31 element is set to zero. Then, from the output of the trigger 32, the formation at the output of the element I 37 of a single potential on the bus P – Pe20 is resolved. The single potential on the bus P means the control mode and the signal on this bus reconfigures the measuring circuits of the entire device and allows the generator 14 to work (Fig. 1). The occurrence of a cool potential at the output of the trigger 32 will block the element I 37 and, on its start, regardless of the register 35, there will always be a zero potential that

2Q that puts the entire device into working mode, and the control mode stops for "

Next, the device operates as follows. At zero address in the counter 29, the verification of the DAC and ADC of the device starts from the ROM with a set of test combinations with the narrowest tolerance zone, if the tolerance zone is not npOH3Oiimo for any of the devices being tested, then on the fault bus leaving the EJHi 28 element, the signal is not on the whits. The calibration cycle on this test code sequence can be repeated.

multiple times as specified by register 5

35

47 numbers, cycles (for example, a set of buttons). This is necessary to confirm the static reliability of errors on a given tolerance zone. If no fault is detected, then trigger

  50 will remain in the zero state. Then, upon completion of a specified number of calibration cycles on a given code sequence by a signal from comparison node 46, through the element

.3 .., which immediately puts the entire device into working mode, thus terminating itself; and the tolerance procedure

Trol .. At the same time, the information on the validity of the device for a given tolerance value is entered into the display register b i.

If during the verification process an error is detected that exceeds the tolerance zone specified by the code set, then from the output of the OR 28 element, the trigger 50 is set to a single state from the output of the OR bus (fault bus). The fault signal is enough to go through only once for so-called verification cycles. If there are several such signals, they only confirm the new state of the trigger 50.

Upon completion of the set number of calibration cycles, the comparison node 46 is triggered. But now the signal passes through the element And 48. This signal will increase the content of the counter 29, which connects the ROM containing the code combinations with a wider tolerance field. The same signal through the delay element 51 will reset the trigger 50, which is now again preparing to capture the error signal. Since the trigger 32 retains its single state and the calibration mode remains, then the calibration over a wider tolerance field and so on is carried out in a similar way.

Eventually, a ROM is connected with such a wide tolerance zone that no error occurs and trigger 32 is reset, which terminates the process.

Claims (1)

Invention Formula Device for interfacing digital computers with analog objects auth.St. No. 1130856, characterized in that, in order to expand the functionality by automatically searching for the tolerance zone of the tested DACs and ADCs by changing the set of test combinations, the permanent storage unit contains a group of permanent storage nodes, a multiplexer, two counters, two triggers , operation mode register, tolerance zone setting register, cycle number register, comparison node, indication register, six AND elements, two OR elements, OR-NOT element, delay element, with the address inputs of permanent storage nodes group s 2569816 form a group of address inputs of a persistent storage unit, the multiplexer output is the information output of the block, the output of the first element And is connected to the control input of the fifth switch, the first and second inputs of the second element And is connected to the control input of the fifth 1Q switch, the first and second inputs of the second element And are connected respectively with the output of the first element IL1 1 and the senior level of the group; outputs of the address decoder, the third input of the second element I is connected to the senior bit of the group, the address inputs of the block, the installation input of the first counter is connected to the installation input of the second counter OR, the first input of the first trigger and is connected to bus initial installation of the device, a single input of the second trigger is connected to the output 25 of the second OR element and, in this case, in the permanent storage unit, the information outputs of the permanent memories of the group nodes are connected to a group of information inputs multiplexed, the control input of which is connected to the output of the second OR element, the first input of which is connected to the output of the third AND element, the first input of which is connected to the output of the first counter; the counting input of which is connected to the output of the fourth element AND and to the input of the delay element, the output of which is connected to the second input of the first OR element, the output of which It is connected to the zero input of the second trigger, the unit and zero outputs of which are connected respectively to the first inputs of the fourth and fifth elements AND, the second inputs of which are connected to the output of the comparison node, the first and second inputs of which are connected respectively to the outputs of the cycle register and the second counter, input the display register is connected to the output of the fifth element I and to the zero input of the first trigger, the elementary output of which is connected to the first input of the first element I, the second input of which is connected to the output of the element and a NOR, a first input of which is coupled to a second input of the third AND gate and to the first output of the register, a second output connected to the second input elemen35 40 45 50 55 17142569818 This OR-NOT both with the first input of the sixth and with the output of the register of setting the zone of the element I, the transducer and the second input of the tolerance, the third output of the register of the third is connected respectively to the work press connected to the third input the second input of the second element OR CM the first element I. te