SU1418814A1 - Device for programming rom modules - Google Patents

Abstract

The invention relates to computing and can be used to record information in ROM semiconductor chips, followed by functional and parametric control. The aim of the invention is to increase the reliability of recording information in the ROM in comparison with the known devices due to the possibility of controlling the amplitude and duration of the programming pulses. In addition, the use of an analog-to-digital converter (ADC) for measuring output signal levels allows rejection of programmed microcircuits according to given output signal levels, which makes it possible to ensure high operating capacity of the ROM. In this case, the rejection can be carried out when the voltage of the microcircuits in the specified tolerance field changes. The device for programming the fixed memory blocks comprises a control block, an address counter, a block of memory for write codes, a block of programmable pulse drivers, and a block of comparison. The goal is achieved by introducing into the ADC device of the switch, the converter of the pulse duration into the voltage and the memory block of the boundary values. 1 il. & (L 00 CX)

Description

The invention relates to computer graphics and can be used to write information to programmable read-only memory (ROM).

The aim of the invention is to increase the reliability of programming due to the periodic monitoring of the parameters of all signals entering the ROM during programming.

The drawing shows a block diagram of a device for programming blocks of permanent memory.

The device contains a control unit 1, a code memory unit 2, a recording unit 3 of programmable pulse drivers, an address counter A, an analog-to-digital converter (ADC) 5, a pulse-to-voltage converter 6, a switch 7, a memory block 8 boundary values of signal levels, block 9 comparison. The drawing also shows the programmable ROM 10, the informational inputs-outputs of the device 11, the address outputs of the device 12, the output voltage of the power supply of the device 13, the recording inputs of the device 14, and the inputs for setting the limit values of the signal levels of the device 15.

The device works as follows.

Before the start of programming, the resetting of the counter 4 of the address, the converter 6 of the pulse duration into voltage, and the elements of the control unit 1 is performed. In blocks 2 and 8 of the recording memory} 1a, information is required. When programming the ROM for each word, the following actions are performed: for each output of the address A counter and all outputs of the formers of 3 pulses, the levels of the signals are monitored using A1Sh 5 and block 9 of the comparison. Controlled outputs are selected by the switch 7 by signals from control unit 1. The same signals are sent to the address inputs of memory block 8, in which the boundary values of the monitored parameters are stored. The codes received from the outputs of the A / D converter 5 and the memory block 8 are compared using the comparison block 9, and the result is transferred to the block 1 control. 1; and 11 1. The counter module 4 is the frequency of the Siformatio capacitance (in words) programmable. The block of shapers of 3 programming pulses includes shapers of power supply voltage pulses, as well as pulses of signals at the inputs-outputs of the ROM, the number of which is equal to the size of the programmable ROM. The number of information inputs of the switch 7 is n m + 2, where ha is the number of address inputs of the programmable ROM unit, and n is the size of the programmable ROM. The number of control inputs of the switch and, accordingly, the address inputs of memory block 8 is Iog2 (n + ni + 2) |

+1 Upon receipt of control sneakers of the switch 7 in the range of 0 ... (p-1), the amplitude of the signals at the information inputs / outputs of the ROM is monitored; P. . . () signal levels at the address inputs of the ROM; n + m is the value of the supply voltage supplied to the ROM; p-It1 + 1 is the amplitude of the signal at the output of the pulse width to voltage converter 6. The code comparison unit 10 has two outputs, and the logical signal O or 1 is taken from the first output if the code from the ADC 5 lies within the limits corresponding to the levels of logical signals read from the programmable memory block C of the second output, a signal is taken that takes the value of logical 1 in the event that the code arriving from the ADC 5 is acceptable for the logic levels O and 1. Next, a reset to the initial state of the converter 6 of the pulse duration to voltage and analysis of the next bit of the code read from the block 2 of the memory are performed. If the analyzed bit of the code is equal to logical 1, then the shapers of the programming pulses of block 3 are started. The amplitude of the programming pulses is monitored using the ADC 5 and the block 10 of the comparison. If the ADC 5 is L, then the number of bits stored in memory block 8 is 2L (lower and upper bounds for each monitored parameter). After the end of the programming pulse, the signal from the transducer–, the pulse duration 6 body to the voltage through the switch 7 is fed to the input of the ADC 5, and (h: what is the result

31A

at the output of the A / D converter 5 is compared with the contents of memory block 8 using comparison unit 10. These actions are repeated for each bit of the programmable word and constitute one programming cycle.

To control the recorded information in each bit of a programmable word, a pulse is applied to the ROM to supply the necessary amplitude and duration of the voltage. The amplitude and duration of the pulse is controlled by the A / D converter 5 of the converter 6 of the pulse duration into voltage and the comparator unit 10. After that, the programmable bit values are compared in the ROM and memory block 2 for storing the codes with the aid of the logic elements of the control block 1. In the event that information is recorded in the programmed word, a transition is made to the next word by incrementing the address counter A by 1 and the transition to the next programming cycle. If the information is not recorded, the programming cycle repeats a specified number of times. The implementation of these actions is carried out using the control unit 1.

The considered device for programming blocks of constant memory provides an increase in the reliability of recording information in comparison with known devices due to the possibility of controlling the amplitude and duration of the signals fed to the ROM. In this case, during the programming process, malfunctions of the programming pulse shaping unit are detected, which eliminates the recording of incorrect information in the ROM. The amplitude and duration of the programmed cix pulses as well as the voltage pulses of the power supply can be varied over a wide range without making changes to the device circuit by changing the codes recorded in the ROM, input

unit in the control unit 1.

Therefore, in comparison with the known programming devices of ROM blocks, the nomenclature of the latter can be significantly expanded. In addition, since the control of the recorded information is performed by comparing the 5 levels of the output signals of the ROM measured by the ADC with the boundary values stored in memory block 8

5 0 5 o

Q g

five

0

g

1A

values, it is possible to reject ROM by output signal levels at different power voltages. Since the programming pulses have a longer duration (from 10 µs to 10 ms) and a duty cycle of 5–20, control and reject operations of the ROM can be performed in the pause between pulses, and control operations of the amplitude and duration of the programming pulses during pulse exposure without slowing the device.

Claims (1)

Invention Formula A device for programming persistent memory blocks comprising a control unit, a storage unit of write codes whose information inputs are input entries of the device, an address counter whose input is connected to the counting output of the control unit, information outputs connected to the address inputs of the code memory unit records and are address outputs of the device, and the transfer output is with an input. End of programming of the control unit; the outputs of the memory block of the write codes are connected to the information inputs of the control unit; the programmable pulse drivers, whose inputs are connected to the information outputs of the control unit, the information outputs are the information inputs / outputs of the device, and the output voltage of the pulse power supply is the output voltage of the device voltage, the comparison unit, the outputs of which are connected to the control inputs of the control unit, characterized by that, in order to increase the reliability of programming, a pulse width converter was introduced into the voltage, the information input of which is connected to you the voltage pulse of the power supply unit of the programmable pulse generators, and the control input - with the output. The initial installation of the control unit, the switch, the information inputs of which are connected to the information outputs and the output voltage pulse power supply terminal of the programming pulse generators, and the information outputs of the address counter and output Prel5 .Ul pulse length to voltage detector, analog-to-digital converter whose input is connected to the switch output, and outputs to the inputs of the first group of the comparison unit, & lok memory of signal level threshold values, the outputs of which are connected to the inputs of the second group of the unit 88146 comparison, the address inputs are connected to the control inputs of the switch and the outputs of setting the addresses of the boundary The -g values of the control unit, and the information inputs are the inputs for setting the boundary values of the device signal levels.