SU1406753A1 - Programmable delay line - Google Patents

Abstract

The invention relates to radio engineering and is intended for use in discrete information processing devices. The programmable delay line (DPS) contains random access memory 1, switch 2, N 3ol-3.N buffer registers and control unit 4, which contains a generator of 5 clock pulses, AND elements 8.9, zero-state deparator 13, counter 7 numbers of the tap, counter 14 of the current address of the record, register 16, subtractor 15, random access memory 17,18, divider 6 frequencies, shaper 10 random time delays, multiplexers 11,12, adder 19 and inverter 20. PLZ provides operational control E tim delay output signals and mode values of the fluctuations of the output signals delays at each independent retraction yl 1. (L

Description

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The invention relates to radio engineering and is intended for use in devices for processing discrete information, for example, in devices for simulating multipath radio channels.

The aim of the invention is to expand the field of application of the programmable delay line by providing on-line control of output delay values and providing for the jitter mode of output delay values at each independent rejection of the delay line.

The drawing shows a block diagram of the programmable delay line.

The programmable delay line contains random access memory (RAM) 1, switch 2, N buffer parallel registers 3.1-3, N, and control block 4.

The address inputs and the control input of RAM 1 are connected respectively to the address and to the first control output of control unit 4, to the second control output of which the control input of switch 2 is connected, whose information input is connected to the output of RAM 1, and the outputs to the inputs of the buffer registers 3.1-3, n.

Control unit 4 contains a generator of 5 clock pulses connected by an output to the input of frequency divider 6, the output of which is connected to the counted input of counter 7 of the tap number with the first combined inputs of elements 8 and 9, and to the clock input of the imager 10 random delays, the output of counter 7 the tap number is connected to the second input of the first multiplexer 11, the first input of the second multiplexer 12, the address input of the shaper 10 case of the delay times and through the zero-state decoder 13 to the second inputs of the first 8 and the second 9 Elements And, respectively, whose outputs are respectively the first and second control outputs of control unit 4, the output of the overflow of the outlet number counter 7 is connected via the counter 14 of the current write address to the first input of the subtractor 15 connected by the output through the register 16 to the address outputs of the control unit 4 . First entry lane

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The first multiplexer 11 is connected to the second input of the second multiplexer 12 and is the address input of control unit 4, the outputs of the first 11 and second 12 multiplexers are connected to the address inputs of the first random access memory 17 and the second random access memory 18, respectively, the outputs of which are combined and connected to the first input of the adder 19, and the combined information inputs are the information inputs of the control unit 4. The control inputs of the first 1 I and second 12 multiplexers are combined and connected to the control input of the first random access memory 17, which is simultaneously the control input of the control unit 4, and through the inverter 20 to the control input of the second random access memory 18, Output shaper 10 random time delays connected to the second input of the adder 19, the output of which is connected to the second input G5,

Programmable delay line works as follows.

The pulses of the generator 5 clock pulses, coming through the frequency divider 6 on the counting input of the counter 7 of the tap number, are sequentially switched to the position from O to IJ. Information from the outputs of the counter 7 of the outlet number in the form of a parallel code through the first multiplexer 11 (when a control is fed to, for example, a low voltage level) is fed to the address inputs of the first random access memory 17 delay values, the address of the memory cell in which binary number (delay coefficient), proportional to the delay time on the i-th line diversion. The overflow pulses of the counter 7 of the tap number are fed to the counting input of the counter 14 of the current write address, transferring it sequentially to the positions from O to M (where M is the number of memory cells of the random access memory l). Information from the outputs of the first random access memory 17 of the delay values and the generator 10 random delay times are fed to the inputs of the adder 19, where the values are added

delays from the first random access memory 17 with 10 random delays generated by the shaper with delay codes based on their sign. From the output of the adder 19, the information goes to the first input of the subtractor 15, the second input of which receives the values from the output of the counter 14 of the current write address.

In the subtractor 15, the address of the location of the random access memory 1, from which the

It is possible to read information for the form of jt-6 frequencies passing through the output signal element for i-ro AND 9 in the presence of a resolution signal, a line retraction. This information is received from the inverse of the output of the zero state delayed relative to the state 13 for the current time, which is determined by the state of the counter 14 of the current write address, by the number of ticks calculated in the adder 19, the calculated cell address is fed to the address inputs of the operational storage device 1 through the register 16. Switch-2 reads-25 and its switching off is not recorded and write to the operational storage occurs. The parallel code from the output device 1 occurs in the switches of the switch 2 is transmitted depending on the state of the counter 7 of the tap number. When information arrives at: the inputs of the debristor 13 are null-, Q goes when they arrive at their control status from the outputs of the counter 7, the current inputs of a single pulse of the diversion clock number for its status from 1 to N from the direct signal of the zero 13 the state of the signal is removed,

prohibiting the passage of pulses

The clock frequency from the divider 6 is the frequency in 1 of the next value of the input through the element AND 8, as a result of the signal. In the state of counter 7, the latter generates a signal that sets the random access memory 1 to read mode.

In the zero state of the counter 7 of the outlet number from the direct output of the decoder 13 of the zero state, a signal arrives at the AND 8 element allowing the single readout jc to pass through it and the reading itself from the opti mal clock pulse whose memory is present operative 1 into the buffer registers 3.1-3.N the repeat storage device 1 is reset N times in one cycle of operation 40

states of the counter 7 numbers of the tap from 1 to N.

For the zero state of the counter 7 of the outlet number, the decoder 13 of the zero state prohibits the passage of clock pulses to the control input

Formation inputs of the buffer registers 3.1-3.N, recording in which the frequency of the output of the element And 8 is zero when the counter 7 is in the zero state, simultaneously with the recording in the operational memory from 1 to N, the buffer registers 3.1 to 3.N are in the mode storage of information. The inputs of the buffer registers 3.1-3, N are the taps of the delay line from which the output signals are taken.

Address determination operations

The recording signal is written to the random access memory 1. At the states of the 7 outgoing number from 1 to N, the subtractor 15 sequentially generates N read addresses from the random access memory 1 of the signal written to it. Random access memory 1 in accordance with the calculated addresses produces

06753

N signals corresponding to the signals on the taps at the current cycle of the delay line. The binary word from the output of the random access memory 1 is fed to the switch 2, which is necessary to increase the load capacity of the random access memory 1 and to switch the parallel binary signals arriving at its input sequentially into the buffer registers 3.1 - 3.N. Switching is performed by clock pulses of control from the output of the divider

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6, the frequencies passing through the element AND 9 in the presence of the signal of the resolution coming from the inverse output of the decider 13 of the zero state for the switch 2 and its switching does not occur. The parallel code from the outputs of the switch 2 enters the input when the control inputs of a single clock pulse arrive at their control.

states of the counter 7 numbers of the tap from 1 to N.

For the zero state of the counter 7 of the outlet number, the decoder 13 of the zero state prohibits the passage of clock pulses to the control input

6, the frequencies passing through the element AND 9 in the presence of the signal of the resolution coming from the inverse output of the decider 13 of the zero state for the switch 2 and its switching does not occur. The parallel code from the outputs of the switch 2 enters the input when the control inputs of a single clock pulse arrive at their control.

the formation inputs of the buffer registers 3.1-3.N, recording in which the frequencies passing through the element 9, in the presence of the resolution signal, come, from the inverse output of the digester 13, the zero state for the switch 2 and its switching does not occur. The parallel code from the outputs of the switch 2 enters the input when the control inputs of a single clock pulse arrive at their control.

in 1 the next value of the input signal. When the state of the counter is 7 but

the frequency of the output element And 8 in the zero state of the counter 7 of the number of the outlet simultaneously with the recording in the operational storage device 1 of the next value of the input signal. When the state of the counter is 7 but

the readout and the matching itself from the RAM 1 to the buffer registers 3.1–3. N is repeated N times in one cycle of operation.

measure from 1 to N, the buffer registers 3.1-3. N are in the information storage mode. The inputs of the buffer registers 3.1-3, N are the taps of the delay line from which the output signals are taken.

Address determination operations

Institute of Delay. The duration of one clock cycle is equal to N periods of the frequency divider 6 pulses. The N-th clock pulse arriving at the retraction counter 7 transfers it from the Nth state to zero, and an overflow pulse is generated that arrives at the counting input of the counter 14 of the current write address and takes it to the next position (t + 1) . Under the new position

counter 7 of the tap number in subtractor 15, the zero code read from the first random access memory 17 (or from the second random access memory 18) of the required delay value is subtracted from the code received from the counter 14. In this cycle, a zero code appears at the output of the generator of 10 random delays, as a result of which the information on the totalizer remains zero. The result at the output of the subtractor 15 is the write address of the input signal for this cycle. Further, the operation of the line is repeated cyclically M times, i.e. until the counter 14 of the current write address is filled, after which the M + 1 pulse at the input of the counter 14 of the current write address brings it to the zero state and the input signal is written again from 0 to M memory cells

During the operation of the delay line to the second random access memory 18, which is in the third output state, direct access is made through the second multiplexer 2, regardless of the state of the 7 offset number. This allows arbitrary rewriting of delay codes in the second random access memory 18 and matching this delay line with virtually any delay code recorder, including microprocessor deactivation. The only time it takes to rewrite the delay codes into the second the operational storage device 18 did not exceed the operation time of the delay line with delay codes recorded in the first operational storage device 17.

When the voltage level control unit 4 changes from low to high, the first 11 and second 2 multiplexers connect their first inputs to the output, the first random access memory 17 switches to the third state output recording mode, and the second random access memory 18 - in the mode of reading the delay codes to the addresses coming from the counter 7 of the outlet number through the second multiplexer 12. The first operation

The memory device is thus ready to overwrite the delay codes.

The capacity of the random access memory device 1 with a parallel to-bit recording of the input data is selected from the following considerations:

 i-t

where is m

- the number of memory cells;

  required maximum

delay;

 - the period of clock pulses at the start of the frequency divider, the same period of the following information. Thus, the range of variation of the delays at the line taps lies in the range from Tuc to. M with discrete step T,. The law of variation of the delay in the specified range is determined by the average values of the coefficients stored in one of the two operative memories of the control unit and the coefficients generated by the shaper of random delay times, and can be selected with any accuracy up to.

Claims (1)

Invention Formula A programmable delay line containing the control unit, random access memory, whose information input is the device input, and the address inputs and control inputs are connected respectively to the address and to the first control outputs of the control unit, the switch whose information input is connected to the output control storage device to the second control output of the control unit, and the outputs are connected to the inputs of the corresponding buffer registers, output The bridges are outputs of the device, and the control inputs are connected to the first control output of the control unit, the control unit contains a clock pulse generator, the first 11 and the second elements AND, the outputs of which are the first and second control outputs of the control unit, and the first inputs of which are connected respectively to direct and IPN outputs of the zero state decoder, the inputs of which are connected to the outputs of the tap number, the subtractor, the first inputs of which through the counter of the current write address are connected to the output of the overflow counter of the tap number, the register, whose inputs are connected to the outputs of the subtractor, and the outputs are address outputs of the control unit, differing from the fact that, in order to heat up the application area, by providing on-line control of the output delay values and providing the fluctuation mode values of delays of output signals at each independent branch of the delay line, the first and second operational memories were entered into the control unit; the outputs of which are combined and connected to the first inputs of the adder, the address inputs to the outputs of the first and second multiplexers, and the combined information the inputs are the information inputs of the control unit. 067538 the outputs of the totalorl are associated with the slow inputs of the Ritshchitel, and the second notes - with the outputs of the random time delays generator, the address drives of which are connected to the outputs of the retraction number, and the clock input to the output of the clock generator and the input of the frequency divider connected to the counting the input of the satellite of the branch number to the second inputs of the first and second elements I, the first inputs of the first multiplexer are combined with the second terminals of the second 15 multiplexers and are addressable. the inputs of the control unit, the second inputs of the first multiplexer are combined with the first inputs of the second multiplexer and connected to the outputs of the counter of the 2Q tap number; the control inputs of the multiplexers are combined and connected to the control input of the first random access memory, which is simultaneously 25 control input control unit, and through the inverter to the control input of the second operational storage 1-1 of the device