SU1405080A1 - Object recognition device - Google Patents

Abstract

The invention relates to automation and computing and can be used in systems for automatic recognition of objects. The purpose of the invention is to expand the domain of application due to the recognition of objects by a combination of parameters. The purpose of the invention is achieved by the introduction of L input registers 1, L, ioic elements containing elements OR-NOT 15 and 16 and OR 17, memory block 8, control unit 9, register numbers K, iacca 10, third comparison circuit II , the third register 12, the register of the characteristic of class 13., the counter address 14 and. logical blocks containing an OR-NOT 15 element, an AND 16 element and an OR 17 element, which allows recognition of objects by a set of parameters. 1 h. item f-ly, 2 ill.

Description

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The invention relates to automation and computing and can be used in automatic recognition systems and objects.

The purpose of the invention. Expansion of the field of application of the device due to the recognition of objects by a combination of parameters.

FIG. 1 is a functional diagram of an object recognition device; in fig. 2 is a control block diagram.

Recognizable object parameters

% /, ..., parameters S {Qi,

represented by vector th

of some

I

spaces

..., QK - 1 De ,, are random variables and can take values in the allowable interval A, /, /, N,, M. Where (is the measurement of space; / is the number of the interval for a given dimension. Except the number parameters describing this, up to.: 1gn () satisfy 1 ratio

i | c, (Y)

where C is the minimum number of parameters; the number of parameters, which deplete them of the required reliability of object recognition.

In this connection, the task of determining the object's belonging to a certain class of objects is reduced to the search for execution. juvenile

eS illV; BUT,

/ eir GT: / 6iv (2)

where jv v is the set of numbers i of intervals with / ,,,,,. M.

The choice of Ai /. (., L,, M determines the reliability of recognition.

In view of the significant power K, during peiiieiiiHi 11ractical tasks, it is necessary to minimize the recognition time, and therefore the constructive JAE is the logic of determining the relative importance to the class by sequential comparison of the parallel set of parameters of the search pattern, ... conditions (2).

In accordance with relation (1), an assumption is made for the recognition of the object by truncating the number of parameters. At the same time, the parameters that are not present at the analysis are not up to date, and they must influence the process of gchchchuzpavan. In this connection, the information: a: i1I on the / -th parameter of an object can take the following form: 1.10 ... 10 - an object parameter; 1.00 ... 00 - parameter is excluded from the analysis; 0.00 ... 00 - no parameter.

Thus, the unit in the old discharge allows you to select the parameters describing this object, and the zero state in the information part (-I o parameter) is perceived as the fact of excluding this parameter from the contour analysis.

The device contains input registers 1., / V blocks of analysis of parameters, the comparison circuit 3, the first element I 4, the second circuit 5

five

.mu 5 comparisons, first b and second 7 registers, memory block 8, control block 9, class number register 10, third comparison circuit II, third register 12, register 13, class indicator, address counter 14, / V logic blocks, containing the element OR - NOT 15, the second element AND 16, the first element OR 17.

The control unit 9 comprises the first delay element 18, the trigger 19, the third element 0 and 20, the clock pulse generator 21, the second 22, the third 23, the fourth 24 and the fifth 25 delay elements, the second e; OR 26.

The device works in the following way.

At the initial moment, the trigger 19 is in the zero state, in memory block 8, the values of permissible intervals of the parameters are stored (/ ,,,, .V,, .V of all objects, as well as the attributes of the classes P / (1, K, in which each position corresponds to the presence or 0 to the absence (-y parameter). The state of the remaining elements of the device does not matter.

With the arrival of the uni si si-pal I lo, the second input of the device on the registers of the block of input registers 1 records information about the parameters of the object being mapped to E as a vector

 q,

arriving at the first input of the device, the counter 14 is set to the zero state, and the trigger 19 is set to the one state through the delay element 18.

The clock pulse generator 21 passes through the element And 20, open high potential of the direct output of the trigger 19, and is fed to the inputs of the recording registers 6 and 7 5 nodes analysis of parameters 2, the first and second information groups of the inputs are set parameters of the reference object from memory block 8 ti, and on register 13 of the class attribute is the prizpak code of the class P. The corresponding parameter address is determined by the value of the address counter 14. Under the action of this clock pulse transmitted through the delay element 22, the parameters of the input object are compared with the reference one in Schemes 3 and 5 of the comparison of the parameter analysis blocks 2. In the event that the rd parameter falls within the allowable limit D (7 // comparison schemes 3 and 5 of the 2nd parameter analysis block 2, they give comparison signals to the first and second inputs of the AND 4 element, to the third input of which a high 0 potential from the highest bit is applied yes the corresponding register register block 1. The signal of the result of the comparison of the ith parameter from the output of the element 4 through the corresponding element OR 17 is output to the corresponding input of the third regimenter 12. In case of exception 5 of the ith parameter from the analysis loop, i. information on the / -th parameter im azanny view corresponding inlet member of the NOR 15 is uro0

five

the extent of the logical unit that passes through the / -th element AND 1Q, opened by the high potential of the high-order / -th input register 1, and through (the element OR 17 enters the corresponding input of the third register 12.

In the case of the absence of the i-th parameter, the logical zero of the j / th input register 1 is written a logical zero, prohibiting the passage of signals through the corresponding J I,

element 16 and the comparison in the / th block 2 of the analysis of parameters is forbidden. The recording of the results of the comparison in the third register 12 takes place with the same clock pulse, which is delayed by the delay 23. The same clock pulse delayed by the delay element 24 permits comparison of the position code of the indicator 1) ect with the reference value m of the prig code of the class by the third comparison unit 1 1, which in the case of the comparison generates a positive search result signal to the external device the first output, under the action of the same signal, the state of the counter 14 is recorded in the register 10 of the class number corresponding to the object class number and the output of this number to the external device via the second output, as well as through the OR element 26 ION trigger 19 into the zero state, prohibiting passage of clock pulses through AND gate 20. The apparatus waits for the arrival of new information

If the comparison does not occur, a positive search result signal is not output, a clock pulse delayed by delay element 25 increases the content of address counter 14 by one, thereby selecting the following reference parameters from memory block 8. With the arrival of the next clock pulse from the generator 21, the operation of the device is repeated. If none of the comparison cycles results in recognition, by overflowing the address counter 14, a negative search result signal is output to the external device on the third output, the same signal through the OR 26 element sets the trigger 19 to the zero state, prohibiting the passage of clock pulses from the generator 21 through the delay element 18. The device is waiting for the arrival of new information.

Claims (2)

1. Devices for recognition of objects, containing the first input register, N parameter analysis blocks, where L is the number of comparison parameters containing the first and second comparison circuits, the first element AND, the first and second inputs of which are connected to the outputs of the first and second comparison circuits, and two registers, the outputs of which are connected to the first information inputs of the first and second comparison circuits, characterized in that, in order to expand R - 5 0 5 About 5 0 5 0 five the ycTpoiicTBa application areas due to the recognition of objects by coBOKyiuiocTn in the metro, a b.yuk of memory has been entered into it, .1 input registers, b. uk control, third comparison scheme, reg) numbers of the hour, third register, K.iacca sign register, address counter and .V logical b.-yukon, containing the elements OR-HH, BTOfxiii y. Ie-ment And and nepBhiii element OR, the first input of the first element OR is connected to the output of the second element AND, the first input of which is connected to the output of the element OR-AND: dy ek ment OR-NOT / -th logical log, where / 1, .V, is connected to the first1 1m output / -I-0 INPUT1-0 register, the second libixo.i of which is connected to the third input of the first e. The first and the second inputs of the irrojioix) of the terminal E, the second entrance of the first terminal OR is connected to the output nepiioi o of the terminal AND, information (the inputs fiei Petrov in, 1 are ne;) B1) 1m entrance devices that control the inputs of the perHCT input ioit include a BTOpiiiM 15 input device, output b. The memory card is connected to the Hcpiioro information boot and the second register | 1 B. b; c) in ana. The parameters of the parameters, nejiBiiiii output b.yuka Unrav, 1 is connected to the control. the entrances of the first and second Reshstrov b. yukov analysis of parameters, second exit b. yuka admin, 1epi connected with yn | a1, 1 by the connecting inputs of the first and second comparison circuits b. yukov of the parameter analysis, the second information inputs of the comparison circuit of the th / th block, 1 of the parameters are connected to the first output of the 1-th input register, the information inputs of the third register are connected to the outputs of the first OR element, the physical blocks, the outputs of the third register are connected the first information inputs of the third comparison circuit, the second information inputs of which are connected to the output of the register of the class feature, the information input of the memory block is connected to the output of the address counter, the control input of the register of the sign of the class The cc is connected to the first output of the control unit, the control input of the third register is connected to the third output of the control unit, the control input of the third circuit is compared to the fourth output of the control unit, the information inputs of the register of the class feature are connected to the outputs of the memory block, the information inputs of the class number register connected to the outputs of the address counter, the output of the third comparison circuit is the first output of the device, the output of the register of the meter of the class is the second output of the device the output of the "Overflow account The address is the third output of the device, the control input of the register of the class number is connected to the output of the third comparison circuit, the first and second inputs of the control unit Reset are connected to the output of the third comparison unit and the output of the address counter overflow, the input of the address counter reset connected to the second input of the device; counting input of the address counter is connected to the fifth output of the control unit; input "Start of the control unit is connected to the second input of the device. 2. The device according to claim 1, characterized in that the control unit comprises five delay elements, a trigger, a third AND element, a second OR element and a clock pulse generator, the output of which is connected to the first input of the third And element, the second input of which is connected to At the trigger output, the forward trigger input is connected to the output of a fifth delay element, the input of which is connected to the "Start block" input. the inverted trigger input is connected to the output of the second element OR, the first and second inputs of which are the first and second inputs of the block reset, the output of the third element I is the second output of the block, the input of the first delay element is connected to the output of the third element AND, and the output is the input of the second delay element is the first output of the block; the output of the second delay element is connected to the input of the third delay element and is the third output of the block; the output of the third delay element is connected to the input of the fourth delay element is the fourth output block, the output of the fourth delay element is the fifth output block.