SU1683030A1 - Queuing system simulator - Google Patents

Abstract

The invention relates to computing and can be used to study the dynamics of the operation of specialized computers of a dynamic architecture that allow automatic multichannel parallelization of tasks. The purpose of the invention is to expand the field of application of the device. A device for simulating queuing systems (QS) contains fifteen AND elements, four OR elements, OR-NOT element, three NOT elements, reversible counter, four comparison circuits, a subtracting counter, two triggers, three totalizing counters, a group of random time delay elements. , a group of triggers, a generator of a random sequence of pulses, a generator of clock pulses, a group of And and the inputs of the task of various conditions and characteristics of the device. The invention allows to expand the field of application of the device by providing the ability to quickly set and change the simulation conditions and characteristics of multi-channel QS. 1 silt, fefESXr

Description

The invention relates to computing and can be used to study the dynamics of the functioning of specialized computers of a dynamic architecture that allow automatic multichannel parallelization of tasks.

The purpose of the invention is to expand the field of application of the device due to the operational setting, monitoring and changing of the simulation conditions and characteristics of multi-channel queuing systems.

The drawing shows a block diagram of the device.

The device contains the first 1, second 2, third 3, fourth 4, fifth 5, sixth 6,

Seventh 7 i / 1 elements, shaper 8 pulses, OR-NOT 9 element, eighth element AND 10, third 11, second 12, first 13 elements NOT, reversible counter 14 queue lengths, first comparison circuit 15, inputs 16 specifying the allowable queue length , inputs 17 sets the number of repetitions of service, subtracting counter 18, first 19, second 20, third 21 elements OR, first trigger 22, group of elements 23 random time delays, group of triggers 24, second trigger 25, start input 26, counter 27 lost for wok, counter 28 received for wok, generator 29 random last pulse sequence, 30 ninth and twelfth AND gates 31, counter 32 time simulation,

the third comparison circuit 33, the inputs 34 of the simulation time, the fourth comparison circuit 35, the inputs 36, the number of lost orders, the 37 inputs, the number of incoming applications, the second comparison circuit 38, the inputs 39, the number of channels, the gold And 40 groups, elements AND 41 of the second group, generator 42 clock pulses, eleventh 43, thirteenth 44, fourteenth 45, fifteenth 46, tenth 47 elements AND, fourth element OR 48, input 49 stops working by the number of lost orders, input 50 stop operation after the time of the mode, the input 51 work stops due to exceeding the queue length and input 52 work stops according to the number of incoming charges.

The presence of a permitting (high level) signal at one or several inputs 49, .... 52 means that it is possible to stop and simulate if the relevant conditions are met: the number of lost loans is exactly or exceeds the allowable, the number of incoming requests is equal to or exceeded the allowed , the queue length is equal to or exceeded the allowed one, the simulation cycle time has elapsed.

The device works as follows.

Before the start of the next simulation cycle, the counters 14, 18, 27, 28, 32, triggers 22, 25 m triples 24 are in zero states. Input 17 records the code of the number of job repetitions when processing one application for a given simulation cycle. On inputs 16, the code of the permissible length of the queue for the wok is entered. The inputs 39 define a code for the number of parallel channels during job processing. At the inputs 37, the code of the permissible number of applications that can be received on this simulation cycle is entered. At inputs 36, the code of the permissible number of un-audited requests on a given simulation cycle is entered. The inputs 34 enter the code of the simulation cycle time. According to the inputs 49 ,, .., 52, a single code is specified depending on the necessary conditions under which the simulation can be terminated, which, in turn, is determined by the simulation objectives for this cycle,

With the arrival at the input 26 of the enabling signal of the start of the simulation, this signal from the output of the open element I 43 enters the installation input of the single state of the trigger 25. The high level of the signal from the single state output of the trigger 25 permits the passage of signals from the generator 42 clock pulses through the element 31

to counter 32, which counts the current simulation cycle time, at the same time the signal from the single-state output of the trigger 25 allows the signals and the random generator 29 from the generator 29 to pass through the element 30 from the output of which, since there is no queue for maintenance yet, and at the output of the comparison circuit 15, the forbidding signal, and all the serving channels are free, the first pulse of a random time sequence through the open elements And 1 and 2 is fed to the input of the installation of a single state igger

5 22, translating it into a single state. The low (prohibiting) level of the sitzl from the inverse output of the trigger 22 closes the AND 2 element, which witnesses. that the concurrently working channels of the service are occupied by the maintenance of the sequence of tasks (algorithms) associated with the receipt of the application in the parallelization mode. Moreover, the parallelization of each task is only for

5 to those channels whose numbers are determined by writing units (high signal level) in the bits of the unit code applied to the input 39. At the same time, the pulse from the generator 29 through the element OR 20 goes to

0 input of the subtractive counter 18, recording the code of the number of repetitions of tasks (algorithms) from the inputs 17. The same pulse through the element OR 19 comes through those elements AND 41, the inputs of which have resolving signals from the inputs 39, which determines the required number of channels parallelization on a given simulation cycle, on the inputs of setting the unit states of the corresponding

0 triggers 24, setting them to single states. At the same time, this impulse from the output of the element OR 19 through the elements 40 opened in accordance with the code stored at input 39, And 40 is fed to the inputs of the corresponding elements 23 random time delays simulating the random service times of the parallelized task (algorithm) over the required number of channels, Through random times equal

0 service times, in each of the parallel channels, pulses appear that bring the corresponding triggers 24 to zero states. As soon as the outputs are zero

The 5 states of all the triggers 24 are set to high levels of signals, and the output of the And 7 elements also shows a high level of the signal. This signal is fed to the subtracting input of counter 18, the leading edge of which from the code value is

the counter 18 subtracts one, which indicates that one task (algorithm) is completed during the servicing process of the application in the parallelization mode. At the same time, the signal from the output of the element And 7 shaper 8 pulses generates a pulse at its output, which through the open element And 6 and element OR 19 is again fed to the inputs of elements And 41 and 40. Thus, the process of simulating the implementation of the task (algorithm) during processing in the channel parallelization mode is repeated the same number of times as determined by the code previously recorded in the counter 18. At the moment when after the next subtraction the code value on the counter 18 becomes equal to zero, at the output of the element OR-HE 9 The signal closing element 6 and opening element 5, the signal from the output of which sets the trigger 22 to the zero state (the passage of pulses of a random time sequence from generator 29 through element 2 is allowed), which indicates the release of the service channels from the previous vki.

In the case when the channels are occupied by servicing the application (sequence of tasks), the pulses from generator 29 do not pass through the element 2, and through the open element 3 they enter the summing input of the reversible counter 14, increasing the value of the code stored in it and thereby imitating the formulation of the incoming stock in the queue for service.

In the case when there are applications in the service queue (a non-zero code is stored on the reversible counter 14), the output of the OR 21 element is a signal that opens the AND 4 element and closes the NOT 12 element AND 5 through the element. In this case when the service is completed in all channels (the code value on subtractive counter 18 is zero, and at the output of the element OR-ME 9 there is a signal that opens the element AND 4 at the output of the driver 8, a signal appears that through the open element 4 subtractive roar of the passive counter, reducing its code value by one and thus simulating the removal of one application from the queue and placing it for service. At the same time, the signal from the output of the AND 4 element through the OR element 20 re-writes the code for the number of repetitions of tasks (algorithms) during maintenance applications in the subtractive counter 18, At the same time, the signal from the output of the element AND 4 enters through the element OR 19 to the inputs

elements 41 and 40, starting again imitating the random service time of the next parallelized task along the required number of channels.

In the case where the length code value

The queue of the queuing at the counter 14 is compared with the code value of the permissible length of the queue; the output of the comparison circuit 15 is a signal opening the AND 10 elements,

0 46 and the element 11 that closes through the element 11. As a result, the pulses from the generator 29 begin to flow to the counter 27, where the code of the number of lost orders is formed due to the absence of places in the queue for 5 woks on a given simulation cycle, if only the second input element And 46 is not given the enable signal from the input 51, which allows the termination of the simulation cycle on reaching the queue length

0 required or larger than specified.

With the beginning of the simulation cycle (trigger 25 in the single state), the pulses from the generator 29 arrive at the summing

5, the input of the counter 28, where the code of the number of incoming service requests for a given simulation cycle is formed.

The end of the simulation cycle occurs in the following cases (when the following events occur).

If the code on the counter 32 is compared (or exceeded) with the code value of the simulation cycle time stored at inputs 34, and there is an enable signal from input 50 and the second input of AND 44. In this case, a high signal is present at the output of the comparison circuit 33 (permitting) level, which through the open element AND 44 and the element OR 48 enters

0 set B zero trigger state 25, low signal level c. the unit output of which closes the elements 31 and 30. If the code of the number received for the simulation per cycle, stored on the counter 28, is compared (or exceeded) with the code of the admissible number from input 37 and input 52 in this case, the high level signal from the output of the comparison circuit 38 through

0 an open element AND 47 and an element OR 48 enters the setting of the zero state of the trigger 25. Next, the operation of the device is similar to the previous case.

If the code of the number of unserved serv- ices formed at the counter 27, is compared (or exceeded) with the code of the admissible number of unserved servants at input 36, and at the input 49 there is a high signal level, then in this case from the output of circuit 35 Comparison High Signal

through the open element L 45 and the element OR ch8 sets the trigger 25 to the zero state.

If the code of the queue for service requests on the counter 14 is compared (or exceeded) with the code of the allowable queue length stored on exhed 16, and a high level signal exists at the input 51, then in this case the high level signal from the output of the comparison circuit 15 the element AND 46 and the element OR 48 sets the trigger 25 to the zero state, which ends the simulation cycle.

The end of the cycle -mg 4ylirovaki occurs at the onset of the earliest of the above abyti.

Formula it is about

A device for simulating queuing systems containing a random sequence of impedances, eight elements AND, three elements NOT, an element OR-NOT, a pulse shaper, a first trigger, three elements OR, a group of triggers, a group of elements of a random time delay, subtracting counter, reversible queue length counter, incoming order counter, lost order counter, first comparison circuit, the output of the first element AND is connected to the first inputs of the second and third elements AND, the output to orogo gate AND is connected to first inputs of first and second OR input of the first unit and trigger the forward and inverse outputs of which are connected respectively one to the second inputs of the second and third AND gates, and a third element connected to the output of summing inputs reversible queue length counter; the subtracting input of which and the second inputs of the first and second elements OR are connected to the output of the fourth element AND, the first SSWM, of which both the first inputs of the fifth and sixth elements I are connected to the output of the pulse former, the input of which and the subtracting input of the counter reading are connected to the output the seventh And element, the inputs of which are connected respectively to the inverse outputs of the group triggers, the bit inputs of the subtracting counter are inputs of setting the number of device service repetitions, the write enable input is subtractive The counter is connected to the output of the second element OR, and the bit outputs of the subtracting counter are connected respectively to the inputs of the element OR NOT, the output of which is connected to the second inputs of the fourth and fifth elements AND and the input of the first element NOT whose output is connected to the second input of the sixth element And the output of which is connected to the third input of the first element OR, the output of the fifth element I is connected to the zero input of the first trigger,

the bit outputs of the reversing queue length counter are connected respectively to the inputs of the third OR element and information inputs of the first group of the first comparison circuit, information inputs

0 of the second group of which are the inputs for setting the allowable queue length of the device, the output of the third element OR is connected to the input of the second element NOT and the third input of the fourth element AND, and the output of the second element is NOT connected to the third input by the fifth element AND the output Equal to the first comparison circuit connected with the first input of the eighth element And and the input of the third element NOT, the output of which is connected to

0 to the first input of the first element I, and the output of the eighth element I connected to the counting input of the lost order counter, characterized by a tag that, in order to expand its area of application by operating, controlling and changing the simulation conditions v, characteristics of multichannel mass systems service, it additionally contains the first and second group of elements And, with

0, the ninth and fifteenth elements AND, the clock pulse generator, the second trigger, the simulation time counter, the fourth OR element, the second, third and fourth comparison circuits, the generator output

5 random sequence of pulses of the order is connected to the first input of the ninth element I, the output of which is connected to the second input of the first element And, the second input of the eighth element And and the counting input of the counter of the incoming application, the bit outputs of which are connected respectively to the information inputs of the first group the second comparison circuit the information inputs of the second group of which are the inputs for specifying the number of incoming applications for the device, and the output Equals the second comparison circuit to the first input of the tenth element And, the second input of which is the input of the device operation stop by the number of incoming orders, and the output of the tenth AND element is connected to the first input of the fourth OR element, the output of which is connected to the single input of the second flip-flop, the inverted output of which is connected to the first eleventh input element And, the second input of which is the device start input, and the output of the eleventh element And is connected to the zero input of the second trigger, the direct output of which is connected to the second input of the ninth element And and the first input two of the eleventh element And, the second input of which is connected to the output of the clock pulse generator, and the output of the twelfth element And is connected to the counting input of the simulation time counter, the discharge outputs of which are connected respectively to the information inputs of the first group of the third comparison circuit, the information inputs of the second group of which are inputs set the simulation time of the device, and the output Equals the third comparison circuit connected to the first input of the thirteenth element AND, the second input of which is the input of After the simulation time expired, and the output of the thirteenth element AND is connected to the second input of the fourth element OR, the third and fourth inputs of which are connected respectively to the outputs of the fourteenth and fifteenth elements AND, the discharge outputs of the counter for the distant wok are connected to information inputs of the first group of the fourth comparison scheme, information inputs of the second

the groups of which are the inputs for specifying the number of lost orders of the device, and the output Equal to the fourth comparison circuit is connected to the first input of the fourteenth

And, the second input of which is the input of stopping the operation of the device by the number of lost orders, the output Equals the first comparison circuit connected to the first input of the fifteenth And element, the second

the input of which is the stop input of the device due to exceeding the queue length, the output of the seventh AND element is connected to the third input of the eleventh AND element, and the output of the first element OR

connected to the first inputs of the elements of the first and second groups, the second inputs of the same elements of the first and second groups are combined and are the inputs of the number of channels, the outputs of the elements of the first

the groups are connected respectively to the device start inputs of the elements of a random time delay of the group, the outputs of which are connected respectively to the zero inputs of the group triggers, the single inputs of which are connected respectively to the outputs of the AND elements of the second group.

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Claims (1)

Claim A device for modeling queuing systems containing a generator of a random sequence of request pulses, eight AND elements, three NOT elements, an OR-NOT element, a pulse shaper, a first trigger, three OR elements, a group of triggers, a group of elements of a random time delay, a subtracting counter, a reversible counter a queue length counter, a counter of received applications, a counter of lost applications, a first comparison circuit, the output of the first element And connected to the first inputs of the second and third elements And, the output of the second th AND gate is connected to first inputs of first and second OR input of the first unit and the trigger, direct and inverse outputs of which are connected respectively to the second inputs of the second and third AND gates, the output of the third AND element is connected to the reversing input of summing queue length counter; ' the subtracting input of which and the second inputs of the first and second elements OR are connected to the output of the fourth element And, the first input of which and the first inputs of the fifth and sixth elements And are connected to the output of the pulse shaper, the input of which and the subtracting input of the subtracting counter are connected to the output of the seventh element And, the inputs which are connected respectively to the inverted outputs of the group triggers, the bit inputs of the subtracting counter are inputs of the job number of repetitions of servicing the device, the input enable recording subtracting Meters withstand connected to the output of the second OR gate. and the discharge outputs of the subtracting counter are connected respectively to the inputs of the OR-NOT element, the output of which is connected to the second inputs of the fourth and fifth elements. The I input of the first element is NOT, the output of which is connected to the second input of the sixth AND element, the output of which is connected to the third input of the first OR element , the output of the fifth element AND is connected to the zero input of the first trigger, the bit outputs of the reverse counter of the queue length are connected respectively to the inputs of the third element OR and the information inputs of the first group of the first a comparison circuit, the information inputs of the second group of which are inputs of setting the allowable queue length of the device, the output of the third element OR is connected to the input of the second element NOT and the third input of the fourth element AND, and the output of the second element is NOT connected to the third input of the fifth element And, the output is equal to the first circuit comparison is connected to the first input of the eighth AND element and the input of the third element NOT, the output of which is connected to the first input of the first AND element, and the output of the eighth element AND is connected to the counting input of the pot counter lost applications, characterized in that, in order to expand the scope of its application due to the operational task, control and change of modeling conditions and characteristics of multichannel queuing systems, it additionally contains the first and second group of elements And, from the ninth to fifteenth elements And, a clock generator pulses, second trigger, simulation time counter, fourth element OR. the second, third and fourth comparison schemes, and the output of the random order pulse generator is connected to the first input of the ninth element And, the output of which is connected to the second input of the first element And, the second input of the eighth element And and the counting input of the counter of incoming applications, the bit outputs of which are connected respectively to the information inputs of the first group of the second comparison scheme, the information inputs of the second group of which are inputs of the job number of applications received by the device, and the output is the comparison circuit is connected to the first input of the tenth element And, the second input of which is the stop input of the device according to the number of applications received, and the output of the tenth element And is connected to the first input of the fourth element OR, the output of which is connected to a single input of the second trigger, whose inverse output is connected to the first input of the eleventh element And, the second input of which is the start input of the device, and the output of the eleventh element And is connected to the zero input of the second trigger, the direct output of which is connected n to the second input of the ninth element And and the first input of the twelfth element And, the second input of which is connected to the output of the clock generator, and the output of the twelfth element And is connected to the counting input of the simulation time counter, the bit outputs of which are connected respectively to the information inputs of the first group of the third circuit comparison, the information inputs of the second group of which are inputs of the task of modeling the time of the device, and the output is equal to the third comparison circuit connected to the first input of the thirteenth element And, the second input of which is the shutdown input of the device after simulation time, and the output of the thirteenth element And is connected to the second input of the fourth element OR, the third and fourth inputs of which are connected respectively to the outputs of the fourteenth and fifteenth elements And, the bit outputs of the counter of lost applications are connected respectively, with the information inputs of the first group of the fourth comparison scheme, the information inputs of the second group of which are inputs of the job number of lost applications devices, and the output is equal to the fourth comparison circuit connected to the first input of the fourteenth element And, the second input of which is the input to stop the operation of the device according to the number of lost applications, the output is equal to the first comparison circuit connected to the first input of the fifteenth element And, the second input of which is the input to stop the device due to exceeding the length of the queue, the output of the seventh AND element is connected to the third input of the eleventh AND element, and the output of the first OR element is connected to the first inputs of the And elements of the first and second groups, the second inputs of the elements of the same name And the first and second groups are combined and are the inputs of the number of channels, the outputs of the elements And of the first group are connected respectively to the start inputs of the device elements of the random time delay of the group, the outputs of which are connected respectively to the zero inputs of the triggers of the group, the unit inputs of which are connected respectively with the outputs of the elements And the second group.