SU1267430A1 - Device for simulating man-machine systems - Google Patents

Abstract

This invention relates to a computing technique for the statistical simulation of man-machine systems. The purpose of the invention is to expand the functionality by limiting the time of the queuing in the queue. The device contains a timer, a random flow generator, a flow counter, a trigger, a trigger, the first and second elements AND, and a group of channels for modeling the work of operators, each of which contains a reversible counter, a prohibition element, AND elements, a NOT element, OR elements, a random block time delay, trigger, received flow meter, served count meter, comparison circuits, adders, register, anas block. Lisa queue for wok. 2 il, JV C 05

Description

The invention relates to computing, in particular, to devices for simulating the human operator of human-machine systems (SMM). The aim of the invention is to expand the functionality of the device by limiting the time of the queuing quota. FIG. The block diagram of the device is shown in FIG. 2 is a block diagram of a queuing analysis quotation. The device contains a random flow generator, a counter 2 of the wok, the first element I 3, three 1-Ger A, block 5 random time delay, timer 6, trigger 7, second element I 8, prohibition element 9, fourth 10 and third AND 11 elements, first adder 12, counter 13 received applications, reversible counter 14, register 15, first 16 and second 17 comparison circuits, second adder 18, first 19 second 20 elements OR, HE 21, first AND 22 and second AND 23 elements, block 24 of the analysis of the queue quotation, counter 25 serviced quotation. Blocks 3-5, 9-21, 24, 25 form a channel for modeling the operation of operators. The block of analysis of the queue for the wok (BAP 24 (FIG, 2) contains a decoder 26, a group of elements OR 27, a group of elements AND 28, a group of counters 29, a group of registers 30, an element 31 of delay, an element OR 32. Reversible counters 14 imitate the queue of the request To the K-th operator. The random time delay blocks 5 mimic the random service time of the application by the operators. The adders 1 calculate the total time of the request service quota. Timer 6 sets the total simulation time, and is also the source of the time stamps. 24 serves to ensure failure and in service, applications whose waiting time in the queue exceeded the Permissible. Counters 25 make a count — the number of requests that the operator served. I Consider the operation of the device in the K-th channel example (, M) 5 where M is the number of operator channels. the initial state on the reversible counter 1A, register 15, counters 2, 13, cy 1mators 12, 18 0, zeros are written. Triggers 4, 7 are in the zero state. The approximate simulation time is dialed on the timer. At the start signal, timer 6 starts counting the simulation time. The time stamps from the second output of timer 6 arrive at the inputs of elements I 8, from the fourth output of timer 6 to the input of EAOH 24 and from the third output of timer 6 with a period T., the control goes to the read inputs of the second adders 18. The Start signal translates trigger 7 into a single condition. A high potential from the direct output of the first trigger 7 opens element 22 for generator 1 pulses of a random stream of pulses that go to counter 2 and element 10 input. If the enabling potential comes from element OR 20 (Kl) -ro channel to the second input of element And 10 of the K-th channel, the pulses from the generator 1 pass through the element 9 of the prohibition of the K-th channel to the counter 13 and the summing input of the reversible counter 14, imitating the occupation of seats in the queue. The signal of the transition from the zero state of the counter 14 to the first (the number 1) passes through the element OR 19, the element AND 3 and starts the block 5 random time delays, simultaneously turning the trigger 4 into one state. In addition, the counter content code (in this case, the number 1) is fed to the input of BAAO 24. Later, if there is a request in the queue (for the zero state of the reversible counter 14), the input potential from the element OR 19 is present at the input of element 3, and Block 5 of a random time delay is triggered by a transition signal from a single state to a zero trigger 4 that has passed through the element 3. The content code of the counter 14 is continuously fed to the input of the block 24. A high potential from the direct output of the trigger 4 opens element 8 and 8 entrance otorrhea time stamp from the timer 6 12 arrive at the first and second adders 18, counting the service time for a channel wok (operator). After a random delay time, block 5 generates a pulse, which throws the second trigger 4 to the zero state, increases the contents of counter 25 by one, and also, after passing through block 24, decreases the contents of the reverse counter 14 by one. Control pulse from the third output of timer 6 It reads the second adder 18. The Tp code of the total channel operation time (operator) for servicing the batch over time Tp is moved to register 15, where it will be stored until the next monitoring impulse. After zeroing, the second adder 18 counts the total channel operation time for the new monitoring period. The second comparison circuit 17 compares the value of the code Tp and T (. D "For, in the case. The comparison circuit 17 generates a signal which, through the OR 20 element, closes the prohibition element 9 for the period until the next pulse to the control and opens the AND 10 element ( K +1 + 1) -th channel (next). Monitoring the total time T, serving for the period between two arrivals of the monitoring pulses and comparing it with the value of T (. Ensures that the operator’s load remains at a level not exceeding D " due to the termination of access to the channel in the channel. The revolving counter 14 (filling all the places in the queue) of the first circuit 16 generates a signal which, through the OR element 20, closes the K 9 channel inhibition element 9 due to the queue filling and opens the AND 10 element (K + 1) -th channel. During the operation of the device, the BAOZ 24 keeps track of the time each customer queued in the service queue. If the waiting time for any application exceeds the allowed one, then block 24 outputs a signal that reduces the contents of the reversible counter 14 by one (i.e. this application is described as outdated and not for maintenance). In this case, under the queuing time of the application in the queue it is considered the time interval from the moment it enters the queue until the beginning of its service. BAOZ 24 works as follows. In the initial state on the decoder 26, the counters 29 and the registers P4 30 recorded zeros. When the application enters the system, the code of the first pass of the reversible counter 14 goes to the decoder 26. The signal from the first output of the decoder 26 passes to the ground, since for the first request the waiting time in the queue is zero. When the next application arrives in the system (if the first application is still in service), the second state code of the reversible counter 14 goes to the decoder 26, and the signal from the second output of the decoder 26 passes through the OR 27.1 element, opens the AND 28L element for the time stamps time stamps from the fourth output of timer 6 begin to arrive at the counting input of the counter 29.1. The timestamp period of the time stamps is chosen so that the time for the memorization of the counter 29.1 to be fully equal to the maximum allowable waiting time for the application in the queue. Thus, in the counter 29.1, the waiting time is counted. As the contents of counter 14 increase (becoming a newly submitted queuing service) by the potential from the corresponding output of the decoder 26, the next element AND 28 for timestamps opens through the corresponding element OR 27. Thus, on the counter 29.1, the waiting time is counted at the first place in the service queue, at the counter 29.2 - the count of the waiting time, which stands at the second place in the service queue, etc., with the contents counter 29.2 is copied in parallel to register 30.1, the contents of counter 29.3 are copied to register 30.2, and so on. If the next application is serviced on time, the pulse from the output of block 5, meaning the 1st end of the service, writes a unit to counter 25, counting the number of servants served by the application, writes off the unit from the reverse counter 14, imitating a decrease in the queue for the wok by one, and reset the counter 29.1. In addition, this pulse, passed through the element RSHI 32, is fed to the input of the delay element 31 and simultaneously zeroes the counters 29. The delay time of the element 31 is selected so that the counters 29 have time to zero-1. After they are zeroed, the delayed pulse from the output of element 31: the delays will go to the inputs of registers 30 and allow the output of information from the outputs of registers 30, after which the contents of register 30.1 will be overwritten by counter 29.1, the contents of register 30.2 - to counter 29.2, etc.

Thus, the counter 29.1 calculates the service waiting time for the application, which is currently in the queue in the first place, the counter 29.2 counts the waiting time for the application in the second place, and so on.

If the waiting time in a queue of a regular application exceeds the allowable one, the counter 29 .1 overflows, the overflow pulse of the counter 29.1 passes through the OR element 32, and deducts a unit from the reversible counter 14. Thus, the application is rejected as outdated. At the same time, the above described process of waiting time codes in the queuing queue,

All channels of the device work in the same way. The operation of the first channel is characterized in that the pulses of the generator 1 through the element AND 22 arrive at the element 9 of the prohibition, i.e. until the queue is filled, queuing pulses pass only into the first channel.

If the barring elements 9 of all channels are closed, either because the operator is busy or because the queue is busy, applications will be rejected.

At the end of the simulation time, the signal from the output of timer 6 transfers trigger 7 to the zero state, closing element 22 and the flow of the request to the channels. The high potential from the inverse output of the trigger 7 enters the inputs O. of elements 11 and 11. The selection of all applications from the queue at the output of elements 11 appears high (since at the exit of the element HE 21 there is a high potential). which is fed to the inputs of the AND 23 element.

The transition junction signal from the single state to the zero channel, the last to complete the service, passes through the HE element 21, the AND 11 element, the I 23 element and enters the stop input of timer 6, fixing the final simulation time. This time is equal to the time previously recruited on the timer, plus the time for the after-servicing of all applications in all channels.

At the end of the simulation, the total number of requests received is counted on counter 2, on counters 13 the number of requests received in each channel, on counters 25 the number served on channels by the channel, on accumulators 12, the channel service time of the request.

Thus, the device makes it possible to profitably improve the quality of the estimation of the activity of an operator with an SMM by simulating his work on servicing the applications taking into account their time in the queue.

Claims (1)

Invention Formula A device for simulating a Human-Machine system containing a random flow generator, trigger, trigger, initial counter, first element, timer, second second element, group of channels for simulating the work of operators, each of which contains the counter of the original application, prohibition element, reversible counter, first, second, third elements AND, trigger, first and second adders, register, first and second elements OR, element NOT first and second comparison circuits and random time delay block, K-th channel for modeling operators work (, M)It contains the fourth element AND, the timer start input is the device start input and is connected to the unit input of the first trigger of the device, the zero input of which is connected to the timer workout output, and the direct output is connected to the first input of the first AND element, the second input of which is connected to the output of the random flow generator of the order, the output of the first element AND of the device is connected to the counting input of the counter for the wok and the information input of the prohibition element of the first channel to simulate the work of the operators and the first Inputs of the fourth element of the K-th channel and the simulation of the work of the operators, in each channel of the work of the operators, the output of the prohibition element is connected to the counter input of the received order counter and the summing input of the reverse counter, the bit outputs of which are connected respectively to the input group of the first element OR the output of which is connected to the input of the element is NOT and the first input of the first element AND of its channel is the simulation of the operator’s work, the output of which is connected to the input of a random time delay block and one the initial trigger input of the operator’s simulation channel, the zero input of which is connected to the output of a random time delay block, and the direct output with the first input of the second element AND its operator’s simulation channel whose second input is connected to the first synchronization output of the timer, the second output element and channel modeling the operator's work is connected to the summing inputs of the first and second adders, the zero input of the second adder is connected to the second clock output of the timer, and The outputs of the second adder are connected respectively to the bit inputs of the register, the bit outputs of which are connected respectively to the first group of inputs of the second comparison circuit, the second group of inputs of which is the installation input of the operator's modeling channel, and the output is connected to the first input of the second RSII element of the second the input of which is connected to the output of the first comparison circuit, the group of inputs of which is connected to the discharge outputs of the reversible counter, the output of the second element OR is connected to the controller in the prohibition element, the inverse trigger output is connected to the second input of the first element, the element output is NOT connected to the first input of the third element, the second input of which is connected to the inverse output of the device trigger, the outputs of the third elements and all channels of the operator’s simulation are connected respectively to the inputs of the second element AND device, the output of which is connected to the timer stop input, the second input of the fourth element AND the K-th channel for modeling the work of operators is connected to the output of the second element OR (K- t) -ro of the channel for modeling the work of operators, the output of the third element AND the PC-channel for modeling the work of operators is connected to the information input of the prohibition element of their channel for modeling the work of operators, in order to extend the functional possibilities 1 (by limiting the residence time queued queue, it additionally contains in each channel the operator’s work simulation of the queued service counter and queuing analysis block containing the decoder, a group of P-1 OR elements, a group of P e And, a group of P counters, a group of P-1 registers, a delay element, an OR element, and the first output of the descrambler is connected to the zero potential bus in the block of analysis of the queue of the queuing unit, the i-th output of the decoder (, P) is connected to the corresponding inputs of all elements of the OR group having a number less than i, (P + +1) -th output of the decoder is connected to the first input of the P-th element AND group, the output (il) -ro of the element OR group is connected to the first input (il) -ro element AND group, the second inputs of all elements AND groups are connected to the third output of the timer, and outputs ale The groups AND groups are connected respectively to cy chiruyush and i inputs of the group counters, the zero inputs of which are connected to the output of the OR element and the input of the delay element whose output is connected to the read enable inputs of all registers, the bit outputs of the i-ro counter of the group are connected respectively to the bit inputs (il) -ro of the register are grouped respectively with bit inputs (il) -ro of the group counter, zeroing the output of the first group counter is connected to the first input of the OR element, in each channel for modeling the work of operators, the output is block A random time delay is connected to the counting input of the counter served by the wok and the second input of the OR element of the queuing analysis block, the output of the OR element of which is connected to the subtracting input of the reversible counter, the bit outputs of which are connected to the decoder of the wok queuing block. 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