SU1405040A1 - Signal generator - Google Patents

Abstract

The invention relates to computing technology, in particular, to devices for controlling test objects. The purpose of the invention is to improve the accuracy of signal generation. The signal generator contains a register 1, counters 2-5, a generator of 6 clock pulses, a generator of white noise 7, trigger 8, blocks 9, 10 of memory, switches 11, 12, digital-to-analog converter 13, element OR 14, element 15 and 17. The goal is achieved by introducing the element OR 14, the elements AND 15-17. 1 il.

Description

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About SP

about

The invention (of PCs; 1 sit is for computational engineering, and for devices intended for controlling test objects.

The purpose of the invention is the increasing accuracy of signal generation.

The drawing shows a structural diagram of the generator signalos.

The signal generator contains a register .1, counters 2-5, a generator of 6 clock pulses, a generator of white noise 7, a trigger 8, memory blocks 9 and 10, switches 11 and 12, a digital-to-analog converter 13, an OR element 14, elements And 15-17, entrance

18 generator control and output

19 generator.

The generator works as follows.

The operation of the signal generator is based on the generation of digital codes for the digital-to-analog converter 13, which come from memory blocks 9 and 10 through switch 12. In this case, two modes of operation of the generator are possible: incidental, which corresponds to the appearance of logical 1 at the output of register 1, and deterministic, which corresponds to the appearance of a logical O at the sixth output of register 1. The generator is prepared for operation by recording the digital signal codes in memory block 9 or 10 by recording the conversion factor in counters 2 and 3. codes can be implemented, for example, from a computer.

When logical 1 appears at the fourth output of register 1, it allows the signal generator to work, and the generator of 6 pulses is started, which leads to the appearance of signals at the overflow outputs of counters 2 and 3, the period of which is determined by the counter conversion factor. Since one counter works on the leading edge of the signal, and the other on the leading edge of the signal, the pulses at the output of counters 2 and 3 will not coincide in time, therefore the sum of two frequencies is formed at the output of the OR 14 element, and 15 is the difference between the two shstot. The difference between the two frequencies is formed as follows: when a signal appears at the output of counter 2, the trigger 8 is reset on the leading edge at 0, and the trailing edge of the signal at the output of counter 3 is set to 1. The signal from the element 5 does not pass from the counter 3 so kaic trigger

8 is set to logical o, so for every pulse of the signal

From counter 2, the pulse is eliminated from the signal from counter 3. Under the control of the signal at the first output of register 1, switch 11 switches the output from element UTI 14 or element 15 to the output of counter 4 or 5. And if at the fifth output of register 1 there is ligic 1, the signal from AND 15 or OR 14 passes to the counting input of counter 4, and the counting input of counter 5 passes the signal from the second output of register 1, which controls the writing of new codes to memory block 10. Counter 4 enumerates the block addresses.

9 in memory and at the output of memory block 9 a signal is generated in digital form. Switch 12 connects the input of a D / A converter to the output of memory block 9. At this time, you can record new codes in memory block 10. With a logical O at the fifth output of register 1, in the memory block 9, new codes are written, and from the memory block 10, reading. In the Deterministic elements mode, And 16 and 17 prohibit the passage of the signal from the overflow output of counters 4 and 5 to the input of the entry of counters 4 and 5. Thus, a complete enumeration of addresses for memory blocks 9 and 10 is performed. In the Random mode, if there is a logical 1, at the output of register 1, the input of the overflow signal of the counter 4 is allowed to enter the input of the counter 4, and the overflow signal is forbidden to the input of the registration of the counter 5, the memory block 9 is in the read mode, and the memory block 10 TI - in recording mode.

When an overflow occurs in the counter 4, the code from the white noise generator 7 is entered into the counter 4. Thus, the codes in memory block 9 are searched from a random starting address, which is equivalent to specifying a random initial phase of the signal and a random sample length. When O occurs at the first output of register 1, information is recorded in memory block 9

Scientific research institute, and utt of unit 10 memory of the cjiyqai iHor o signal.

Invention Formula

A signal generator containing a register, four counters, a clock generator, a white noise generator, a trigger, two memory blocks, two switches, the register input connected to the generator control input, a direction selection output of which is connected to the control input of the switch, the second control input - Lenin of which is connected to the output of the register strobe, the input of the entry of the first counter is connected to the output of issuing information of the register, the output of the protection permission of which is connected to the start input of the clock pulse generator, The output of which is connected to the counting inputs of the first and BTopoj o counters, the information input of the first memory block is connected to the information input of the second memory block, the outputs of the third and fourth counters are connected to the address inputs of the first and second memory blocks, the outputs of which are connected to the first and second information inputs of the second switch, the output of which is connected to the output of the generator, about t-l and h and 1C and with the fact that, in order to determine the accuracy of signal generation, an element is introduced into it

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ABOUT

IPI and three elements AND, let's take the input of the second counter input is connected to the information input of the first memory block and the output of register information output, the memory block selection output is connected to the account control input of the first switch, the first input of the first and second AND elements, the control inputs of the first and the second memory blocks and the control input of the second switch, the output of the selection of the mode of the register is connected to the second inputs of the first and second elements AND, the third inputs which are connected respectively to the overflow outputs of the third and the fourth counters, the counting inputs of which are connected to the first and second outputs of the first switch, respectively, the code of the white noise generator is connected to the inputs of the recording of the third and fourth counters, the control inputs of which are connected to the outputs of the first and second elements, the overflow output of the first counter is connected to the first input the OR element and the reset input of the trigger, the installation input of which, the second input of the OR element and the first input of the third element AND are connected to the overflow output of the second counter, the output trigger and connected to the second input of the third element AND, the output of which and the output of the element OR are connected to the first and second information inputs of the first switch.

Claims (1)

Claim A signal generator comprising a register, four counters, a clock pulse generator, a white noise generator, a trigger, two memory blocks, two η switches, the register input being connected to the generator control input, the direction selection output of which is connected to the control input of the first switch, the second control input - the purpose of which is connected to the output of the register strobe, the input of the first counter is connected to the output of the register information, the output of which start enable is connected to 2 (the start input of the clock c, the output of which is connected to the counting inputs of the first and second counters, the information input of the first memory block is connected to the information input of the second memory block, the outputs of the third and fourth counters are connected to the address inputs of the first and second memory blocks, the outputs of which are connected to the first 3 and the second information inputs of the second switch, the output of which is connected to the output of the generator, with the exception of the fact that, in order to increase the accuracy of signal generation, an element is introduced into it OR and three AND elements, with the input of the second counter entering connected to the information input of the first memory block and the output of register information, the memory block selection output connected to the account control input of the first switch, the first input of the first and second elements AND, the control inputs of the first and second blocks memory and control input of the second switch, the output of the choice of the register mode is connected to the second inputs of the first and second elements And, the third inputs of which are connected respectively to the overflow outputs of the third and four counters, the counting inputs of which are connected to the first and second outputs of the first switch, respectively, the output of the white noise generator is connected to the inputs of the third and fourth counters, the control inputs of which are connected to the outputs of the first and second elements AND, the overflow output of the first counter is connected to the first input of the element OR and the trigger reset input, the installation input of which, the second input of the OR element, and the first input of the third AND element are connected to the overflow output of the second counter, the trigger output is sub It is connected to the second input of the third AND element, whose output and the output of the OR element are connected to the first and second information inputs of the first switch.