SU1403350A2 - Single pulse shaper - Google Patents

Abstract

The invention can be used in devices of pulse engineering, automation and computer technology. The invention improves the stability of the formation of output pulses, which is achieved by prohibiting the resetting of the input 5 and intermediate 6 triggers for the duration of the formation of the output pulse. The device also contains a triggering trigger 1, opening and closing contacts 2 and 3 of the switch 4 of the logic signal, the output trigger 7, the elements AND 8-12, the element OR 13, the resistors 14, 15 and 16, the capacitor 17, the bus 18 clock pulses, the output bus 19, the power supply bus 20 of a single logical level and the common bus 21 of a zero logic level. On the bus 19, an output pulse is generated, the duration of which is equal to the duration of the low level clock pulse. The device eliminates the possibility of reducing the duration of the output pulse, if the holding time of the triggering trigger is shorter than the duration of the clock pulse, since the output pulse for the duration of its duration prohibits the passage of a low level signal through the And 12 element. .j i (About

Description

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The invention relates to a pulse-i HJpft technique and can be used in | devices automation and computing.

The aim of the invention is to increase the stability of the formation of the output pulse by prohibiting the resetting of the input and intermediate triggers at the time of the formation of the output pulse.

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The drawing shows the electrical-functional scheme of the proposed device.

Single pulse shaper keeps triggering trigger 1, disconnecting and closing contacts 2 and 3 Switch A of the logic signal, input, intermediate and output - tiggers 5, 6 and 7, first, second, third, fourth and additional e-elements AND IS-HE 8 , 9,10, 11, and 12, ele-j 1 TNT or 13, the first, second, and additional | resistor 14, 15, and 16, the capacitor-25 sensor 17, the bus 18 clock pulses, output bus 19, the bus 20 power | and (single logical level) And common bus 21 (zero logic level), with zero and one on the n inputs of trigger 1 connect The contacts 2 and 3 of switch 4, the switching contact of which is connected to bus 21, contacts 2 and 3 are connected via resistors 14 and 15 to the central bus, the inverse output of flip-flop 1 is connected to the first input of the element 12, the input of which is connected to the output of the element 11, the output of the element 12 is connected to the first input of the element 13, the second input of which is connected via the resistor J6 to the bus 20 and through the capacitor 17 to the bus 21, the output of the element 13 is connected to the zero inputs of the flip-flops 5 and 6 and the input element 8, the Second input of which is connected to the bus 18, the output element 8 connected to one single input of trigger 5 and to the first input of element 9, the second input of which is connected to the forward output of the trigger ii epa 5, the output of element 9 is connected to the single input of the trigger bis first input of the element 10, the second input of which is connected to direct output of the trigger 6, to the zero input of the trigger 7 and to the first input of the element 11, the element of the IO element is connected to the single input of the trigger 7, the inverse output of which is connected to the second in

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do element 11, the output of which is connected to the bus 19.

The shaper single pulse works as follows

At the initial moment of time, when the supply voltage is applied to the device, at the second input of the element 13 (for the time of charging the capacitor f7) a low level signal is generated, which from the output of the element 13 goes to the zero inputs of the flip-flops 5 and 6, sets them to zero condition. Thus, the shaper is set to its initial state, in which a low-level signal is received from the pin 2 of the switch 4 to the zero input of the trigger 1, and a high-level signal to the single input from pin 3 via the resistor 15. At the same time, trigger 1 is in zero frequency. From the inverse output of trigger 1, a high level signal arrives at the first input of element 12, the second input of which also receives a high level signal from the output of element 1I. The low level signal from the output of element 42 through element 13. enters the first B. Output of element 8, prohibiting the clock from the j 18 bus through element 8, as well as to the zero inputs of the flip-flops 5 and 6, keeping them in zero state In this case, the signal from the output of the trigger 6 keeps the trigger 7 in the zero state.

When contact 2 is opened and contact 3 is closed, trigger 1 is set to one. The low level signal from the inverse output of the trigger I is fed to the first input of the element 12. From the output of the element 12, the high level signal is received. to the first input of the element 13, to the second input of which through the resistor 16 from the bus 20 the post signal is also high. From the output of element 13, the high level signal goes to the zero inputs of flip-flops 5 and 6 and to the first input of element 8, allowing the clock pulses to pass through element 8, the high-level clock pulse passes through element 8 and converts the trigger 5 to one state permits the passage of clock pulses through element 9; low level clock pulses (on bus 18) pass through element 9, on the front of the first of them is translated

In unit state 1, the rigger 6, from the output of which the high level signal goes to the zero input of the trigger 7 and to the inputs of the elements 10 and 11, At the other input of the element 11 there is already a high level signal from the inverse output of the trigger 7. At the same time, the output of the element P set the element 11 and keeps a high level signal at its output. Setting the trigger 6 to the zero state is set to the zero state of the trigger 7, on the inverse output of which a high level signal is set, which enters the input of the element 11, the device

The signal is a low level, which is reset. So

It enters the bus 19 and the input of the element 12, from the output of which a high level signal passes through the element 13 to the first input of the element 8 and the zero inputs of the flip-flops 5 and 6 and is held on them until the end of the output pulse, thereby prohibiting the resetting devices in case of trigger setup

I in the zero state -. The next highest level clock (on bus 18) that follows this time passes through element 10 and sets trigger 7 to one state. In this case, the output element

I1 is set to high again.

who level

Loss of opening of contact 3 and closing of contact 2 of switch 4 is set to the zero state trigger 1, from the inverse output of which a high level signal comes

at the first input of element 12 and in the case of NAND, with the connected sequence at the second input of the signal, 35 NI and OR are included

At any level coming from the output of element 11 and indicating the end of the output pulse, the low level signal from bus 19 through element 13 transfers the triggers 5 and 6 to the zero state.

The low level signal from the trigger output 6 is fed to the second input

Formula

Thus, a single pulse is formed on the output bus 19, the duration of which is equal to the low-level clock pulse, while eliminating the possibility of reducing the output pulse duration if the holding time of the trigger trigger in the unit state is shorter than the low-level clock pulse its duration prohibits the passage of a low level signal through element 12.

the invention

Shaper single pulses auth.St. No. 1205274, about tl and h ay - y and so that, in order to increase the stability of the formation of the output pulse, an additional resistor, a capacitor, an OR element and an additional element are introduced into it

between the inverse output of the triggering trigger and the zero input of the intermediate trigger, the second input of the NAND element is connected to the output bus, the second input of the Sh1I element is connected via an additional resistor to the power bus and through a capacitor to the O6 bus.

Claims (1)

The claims to the Shaper of single pulses by auth. No. 1205274, characterized in that, in order to increase the stability of the formation of the output pulse, an additional resistor, capacitor, OR element, and an additional AND-NOT element are introduced into it, while the AND-NOT and OR elements connected in series are connected between the inverse output of the trigger and zero input of the intermediate trigger, the second input of the AND element is connected to the output bus, the second input of the OR element is connected to the power bus through an additional resistor and through the capacitor to the bus bar. Compiled by A. Sokolov Editor Y. Sereda Tehred M. Khodanich Έορρεκτορ G. Reshetnik Order 3004/55 Circulation 928 Subscribed VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and printing company, Uzhhorod, st. Project, 4