SU1401556A1 - Phase increment discriminator - Google Patents

Abstract

The invention relates to radio engineering. To expand the phase inquiries, N-1 channels, identical to the 1st channel, are entered into the device. L - 1 el-tov 2, 2yV-3 detractors 5. The input signal is fed through the input bus 1 to the 1st input of the phase detector (PD) 3i, which is part of the 1st channel and consists of the PD 3i low pass filter (LPF) 4, and through the el-2: - on the 2nd channel of the device. In each PD 3, two signals are multiplied, one of which is time delayed by T to provide a phase angle of the piece, close to 2 liters ;; 4l, etc. (with - the frequency of the input signal). With the help of low-pass filter 4, a low-frequency component of this product is allocated in each channel, which is proportional to the increment of the 1st order of phase increments of the input signal. The low frequency increment component of the 2nd order is formed at the output of the subtractor 5i. To isolate the increments of the .V-ro order, a subtraction operation is performed on the increment of the (L -1) -th order. 1 il. about € (L from 4 about NBiA 01 01 Ci

Description

The invention relates to radio engineering and can be used in frequency stabilization systems as an error meter.

The purpose of the invention is to expand the range of phase increments.

The drawing shows the structural electrical circuit of the discriminator for phase transitions.

The discriminator phase increments contains the input busbar 1, / V delay elements 2, L phase detectors (PD) 3, .V low-pass filters 4 (LPF), (2 / V-3) subtractors 5, where N- is the number of phase discriminator channels increments each

increment of the 1st order of phase increments of the input signal. The low frequency increment component of the 2nd order is formed at the output of the subtractor 5i. To isolate the jV-ro increments of the order, a subtraction operation is performed on the increments of the (/ V-1) -th order.

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Claims (1)

Invention Formula A phase increment discriminator containing a first channel consisting of a serially connected phase detector and a low-pass filter, the first of which consists of a sequential state. The input of the phase detector is the input of a single phase detector and filter channel, the low-pass filter output, where the first input of the phase detector is the channel input and the output of the low-pass filter is the channel output and .1. The discriminator phase increments works as follows. The input signal is fed through the input bus 1 to the first input of the phase detector 3 |, which is part of the first channel of the phase increment discriminator and consists of series-connected PD 3 | and low pass filter 4 |, and through element 2 | delays at its second entrance. Through the delay element 2i, the input signal is fed to the second channel of the phase increment discriminator consisting of PD 32 and LPF 40. Each PD 3 multiplies two signals, one of which is delayed by the time τ of delay element 2 to provide the phase angle of cells, close to 0; 2l ;; 4l, etc., where O) is the frequency of the input signal. With Pomonhue LPF 4, each channel is allocated a low frequency component of this product, which is proportional to 25 the channel output, as well as a delay element, the input of which is connected to the first input of the phase detector, and the output to the second input of the phase detector of the first 20 channels, characterized in that, in order to expand the range of measurement of phase increments, N-1 channels are introduced into it, where, identical to the first, V-1 serially connected delay elements, 2 / V-3 subtractors, and the outputs of the previous and the subsequent channels are connected to the inputs of the subtractors, starting from the first to (N-1) -th, respectively, whose outputs are connected to the inputs of the subtractors, starting with yV-ro according to the ladder diagram, respectively, Q, and the input of the second delay element is connected to the second input first channel and first detector at the phase detector input of the second channel, the second delay element output is connected to the second input of the second phase detector 25 channels, the output / V-ro of the delay element is connected to the second input of the phase detector of the yV-ro channel. increment of the 1st order of phase increments of the input signal. The low frequency increment component of the 2nd order is formed at the output of the subtractor 5i. To isolate increments of the jV-ro order, a subtraction operation is performed on the increments of the (/ V-1) -th order. ten Invention Formula five the channel output, as well as a delay element, the input of which is connected to the first input of the phase detector, and the output to the second input of the phase detector of the first 0 channels, characterized in that, in order to expand the range of measurement of phase increments, N-1 channels are introduced into it, where, identical to the first, V-1 serially connected delay elements, 2 / V-3 subtractors, and the outputs of the previous and Subsequent channels are connected to the inputs of the subtractors, starting from the first to (N-1) th, respectively, whose outputs are connected to the inputs of the subtractors, starting with yV-ro according to the ladder diagram, respectively, and the input of the second delay element is connected to the second input of the first channel and first input of the phase detector of the second channel, the second delay element output is connected to the second input of the second phase detector 5 channels, the output / V-ro of the delay element is connected to the second input of the phase detector of the yV-ro channel.