SU1185565A1 - Frequency discriminator - Google Patents

Abstract

A FREQUENCY DETECTOR containing serially connected input attenuator, phase inverter, first adder and first amplitude detector, serially connected second adder and second amplitude detector, as well as a delay line connected between the combined input of the second adder with the input of the attenuator and the second inputs of the first and second adders, connected in series the third and fourth adder, the output of which is connected, to the control input of the input attenuator, as well as the subtraction unit, the output to Expensively, it is an output of a frequency detector, characterized in that, in order to increase the detection accuracy under the influence of parasitic amplitude modulation, sequentially connected and connected between the output of the subtractors and the second input of the fourth adder are introduced into it, the first (and The left and second inputs of the third adder and the subtraction unit are connected with to the output of the first and second amplitude detector, respectively.

Description

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Fig. 1 The invention relates to radio engineering and can be used in radio receiving and measuring devices. The purpose of the invention is to improve the detection accuracy under the influence of spurious amplitude modulation. FIG. 1 shows a structural electrical circuit of a frequency detector, FIG. 2 - diagrams of it. work. The frequency detector (BH) contains an input attenuator 1, a phase inverter delay line 3, the first and second adders 4 and 5, the first and second ampere detectors 6 and 7, the third adder 8, subtraction unit 9, quad 10, voltage divider 11 the fourth adder 12. The frequency detector operates as follows. Let the input attenuator 1 receive the signal Ug E Sin u) t .. At its output there will be a signal ..np)) t, where K (and, the transmission coefficient of the input attenuator 1 depending on the control voltage. At the output of line 3 delay voltage (I / ,, p) s-, nu) (ir), where T is the delay time. At the outputs of the first and second summers A and 5. (, Np)) (- t- |), 2-U /,), (t- |) After linear amplitude detection by the first and second amplitude detectors 6 and 7 - at the output Block 9 of the subtraction signal has the form (Fig. 2d) u.-2eK (4h1HJ-hfl), and at the output of the third adder 8 (Fig. 25). (hf The static characteristic of the frequency detector (Fig. 3a) is periodic, symmetric from 652 relative to the transition frequency defined by the expression u),). where n Oif ... However, with closed feedback (the control input of the input attenuator 1 is connected to the output of the fourth adder 12), the variable voltage from the output of the third adder 8 (Fig. 25), which is control for the input attenuator 1, through the fourth adder 12 leads to a change in the transmission coefficient of the input attenuator 1 depending on the frequency of the input signal, which leads to significant distortions m. To eliminate the voltage change at the output of the fourth adder 12, its second input receives a compensating signal (Fig. 2c) formed from the output signal of the frequency detector using a quadrant 10 and voltage divider 11 (Fig. 2d), 4U-r 2EK ( ; ,, J COS + K cos From Fig. 2d, it can be seen that after adding a compensating signal, the change in voltage at the output of the fourth adder 12 when the frequency of the input signal changes is much less than at the output of the third adder 8 (Fig. 25). At the optimum coefficient transmission divider eg. K 0.368 d The maximum voltage variation is compensated. The voltage change does not exceed 1.5% over the entire input frequency range, while if there is no compensating signal, this change reaches 40%. Eliminating the dependence of the voltage on the input attenuator 1 on the frequency of the input signal significantly increases the linearity of the detection. At the same time, the noise immunity of the frequency detector against the influence of the parasitic amplitude modulation of the input signal is high.

Claims (1)

A FREQUENCY DETECTOR, comprising a series-connected input attenuator, a phase inverter, a first adder and a first amplitude detector, a second adder and a second amplitude detector connected in series, as well as a delay line connected between the combined input of the second adder with the output of the input attenuator and the second inputs of the first and second adders, the third and fourth adders connected in series, the output of which is connected to the input 'of the input attenuator control, as well as a subtraction unit, the output of which is an output of a frequency detector, characterized in that, in order to increase the accuracy of detection under the influence of parasitic amplitude modulation, a quadrator and a voltage divider are introduced in series and connected between the output of the subtraction units and the second input of the fourth adder, with the first and second inputs the third adder and the subtraction unit are connected to the output of the first and second amplitude detector, respectively. FIG. 1