SU1399740A1 - Variable priority device - Google Patents

Abstract

The invention relates to computing and can be used in computing devices for interrupting programs. The goal of choosing is to expand the functional capabilities of the device by setting any query to any priority. theta. The device contains a group of re-- | gistrov 9, comparison block 11, decryptors corpse 10, query register 2, trigger 3, group of elements AND 4, element OR-NOT 5, two elements AND 6, encoder 7 and decoder 8 V device. You can quickly change device priorities , requests i from which are received for service. 2 Il.

Description

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The invention relates to computing and can be used in devices for interrupting programs, f

The purpose of the invention is to expand the functionality of the device by providing the ability to set any priority to any request, 10

Figure 1 shows the structural diagram of the device; Fig. 2 is a block diagram of a comparison block. The device contains shift register 1, register 2 requests, trigger 3.15 group of elements AND 4, element OR - NOT 5, elements AND 6, encoder 7, decoder 8, group of registers 9, group of decoders 10, block 11 of comparison, group of request inputs 12 devices, a group of inputs 13 of the device’s highest priority code, inputs 14, device shift directions, a group of inputs 15 device request priority codes, a group of information output devices 16, a device clock input 17, decoder outputs 18 and outputs 10 19 register 1.

Block 1 I form groups of elements AND 20 and elements OR 21.30

The device works as follows.

According to the subscriber numbers, the service request signals are received at the inputs 12 of the device to the register 2 and 5 requests, where they are fixed positionally, and the priority codes of these subscribers are received respectively by the groups of inputs J5 to the registers 9, and each should have different priorities. theta. In the process, priorities may vary. The code of the highest priority of the post at a given time. , feeds on the device inputs 13 to the decoder 8, while the signal 5 corresponding to the given priority number is fixed positionally in register 1, the signal determining the viewing direction of priorities arrives at the corresponding input 14 of the device and sets the trigger 3 to the required condition. All this is done in software. The trigger (direction of shift) 3 opens one corresponding element AND 6 at a time. The priority codes from registers 9 are sent to decoders .10, from which they are sent to groups of inputs of comparison blocks II, to the last inputs of block 11

feeds the I shift register. The comparison signal from one of the outputs of the comparison block 11 opens the corresponding element AND 4. In case there is no request from the device having a priority equal to the highest one at the moment, the outputs of the AND 4 group of elements are no signal, the element OR NOT 5 remains open and the signal with its output opens the corresponding element And 6 through the third input. The clock pulses from input 17 follow through the corresponding open element I 6 to the control input of the shift register 1. The shift of the register contents in a given direction begins. The shift is carried out until the output signal of the group of elements 4 does not receive the signal of the presence of a request that arrives at: b; the input of the encoder 7. At the outputs of the encoder 7, the device code appears, the request of which is received for service. The code on outputs 16 can be used as a modified part of the address. When a signal appears at the output of one of the AND 4 elements, the OR-NOT 5 element prohibits the passage of clock pulses through the corresponding AND 6 element until the end of the service request, as evidenced by the removal of the request from the serviced device from the registry 2 requests.

Formula of the invention The variable priority device containing an OR-NOT element, an encoder, a request register, a shift register, a group of AND elements, a decoder, two AND elements, a trigger, and the group of information inputs of the request register is a group of request inputs. The device's terminals, the direct and inverse outputs of the trigger are connected to the first inputs of the first and second And elements, respectively, the second inputs of which are; left connected to the clock input of the device, the outputs of the first and second elements I are connected respectively to the first and second inputs of the shift register shift, the first input of each element AND group is connected: With the same output register of the request, the outputs of the elements AND groups are connected to the group encoder inputs, the outputs of which are a group of information outputs of the device and connected to the input group of the element OR NOT

the output of which is connected to the third inputs of the first and second elements AND the group of inputs of the device's highest priority code is connected to a group of decoder decoders, the group of outputs of which is connected to the group of information inputs of the shift register, the first and second inputs of the direction of the shift of the device are connected respectively to the single and zero inputs trigger, characterized by the fact that, in order to expand the functional. capabilities by providing the ability to assign any request any priority, it contains

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a group of registers, a group of decoders and a comparison unit, the groups of information inputs of the register block are groups of inputs of device priority codes, the group of outputs of each register of the group is connected to the inputs of the decoder of the same name; v groups, the group of outputs of each group decoder is connected to the same group of inputs of the comparison block, the last group of inputs of the block is compared to the outputs of the shift register, each output of the comparison block is connected to the second input of the homonymous element of AND group.

Claims (1)

SUMMARY OF THE INVENTION A variable priority device comprising an OR-NOT element, an encoder, ~ a request register, a shift register, a 40 group of AND elements, a decoder, two AND elements, a trigger, the group of information inputs of the request register being a group of request device inputs, direct and inverse 45 the trigger outputs are connected to the first inputs of the first and second elements And, respectively, the second inputs of which are connected to the clock input of the device, the outputs of the first and second 5θ elements And are connected respectively to the first and second inputs the shift register control odes, the first input of each AND element is connected to the request register output of the same name, the outputs of the AND groups are connected to the encoder inputs group, the outputs of which are the device information outputs group and connected to the OR-NOT element inputs group, the output of which is connected with the third inputs of the first and second elements AND, the group of inputs of the code of the highest priority of the device is connected to the group of inputs of the decoder, the group of outputs of which is connected to the group of information inputs of the shift register, the first and second inputs of the device’s direction of shift are connected respectively to jq with single and zero inputs of the trigger, characterized in that, in order to expand the functionality by providing the ability to specify any request of any priority, it contains a group, registers, a group of decoders and a comparison unit, moreover, groups L information inputs of the register block are groups of inputs of device priority codes, the group of outputs of each group register is connected to the inputs of the group decoder of the same name, the group of outputs of each group decoder is connected to the group of inputs of the comparison unit of the same name: the last group of inputs of comparison block ^{1 is} connected to the outputs of the shift register , each output of the comparison unit is connected to the second input of the same element AND group. Fiz. 2