SU1397860A1 - Device for checking multichannel digital apparatus - Google Patents

Abstract

The invention relates to instrumentation engineering and serves to extend the functionality of the device. The device contains a control unit 3, a generator of 4 tests, multiplexer 5, demulti-. the plexer 6, the selector 7, the signature analyzer 8 of the comparison unit 12, the indicator 9 and the block 21 of the range switches. Introduction, blocks 11 and 13 of the sensors of the initial and final reading zones, a two-input element AND 10, a comparison unit 14, a block 15 OR elements, a block 16 AND elements, a selector 17, a two-input element OR 20, full switches 18, respectively control and block 19 of channel switches provides selective control of individual channels of multichannel digital equipment or selected words of the control test. 6 Il. (L

Description

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The invention relates to instrumentation engineering and can be used to monitor digital equipment consisting of channels of the same type, each of which can operate in full or in part. A special case is hardware consisting of fixed memory nodes built on 556 series microchips, in which part of the microchips is not used at all or some of the addresses in them are not used.

The purpose of the invention is to expand the functional capabilities of the device by selectively monitoring individual channels of multichannel digital equipment on selected words of the control test.

FIG. 1 shows a device for controlling multichannel digital equipment; in fig. 2 - control unit; in fig. 3 - multiplexer; FIG. 4 shows a demultiplexer; in fig. 5 - the first selector; Fig. 6 shows a block of target points of the zone with blocks of comparison.

The device for controlling multichannel digital equipment 1 divided into separate channels 2.1-2.k contains a control block 3, a test generator 4, a multiplexer 5, a demultiplexer 6, a first selector 7, a signature analyzer 8, an indicator 9, a two-input element AND 10, a block 11 setters of the initial zone of the gateway, the first comparison unit 12, the block 13 of the end readout zone adjusters, the second comparison block 14, the block of 15 elements OR (three-input), the block of elements AND 16, the second selector 17, the switch 18 of the control completeness, the block 19 of channel switches, dvuhvh dovy OR gate 20, the control unit 21 switches ranges.

the input of which is connected to the output of the two-input element I Yu, and the output to the input of the indicator 9. The group of the first outputs of the control unit 3 is connected

The control unit 3 (FIG. 2) contains an OR element 22, a 1K flip-flop 23, an AND 24 item, an OR 25 element, a 1K-flip-flop 26, an And 27 element, a counter 28,

decoder 29, button 30, RS flip-flop 31.50 with the first inputs of the first 12 and second transformer 32 pulses, element OR 33, counters 34 and 35, decoder 36, button 37, generator of 38 cycles.

14 blocks of comparison. The outputs of the 4 test generator are connected to the second inputs of the multiplexer 5, the outputs of which are connected to the terminals for connecting the Test generator 4 in the general case of the inputs being checked digital is a permanent memory with a test program written in it for m outputs and 1 binary bits Dov addresses.

equipment 1. The demultiplexer 6 with its second inputs is connected to the terminals for connecting the outputs of the tested digital equipment 1, and output 0

0 5

0

The multiplexer 5 (Fig. 2) consists of k identical T-input elements And 39.

The demultiplexer 6 (Fig. 4) consists of k of the same type of n-input elements AND 40 and of n k-input elements OR 41.

The selectors 7 and 17 (FIG. 5) are respectively the n and k elements 2I-OR 42.

Signature analyzer 8 is a shift register with feedback through a modulo-two addition scheme.

The units 11 and 13 setting points of the zone (Fig. 6) consist of k groups of elementary switches 43 with S pieces per group.

Comparison blocks 12 and l4 consist of k S-bit comparison elements 44.

The blocks of elements AND 16 and OR 15 consist respectively of k elementary two-input and three-input elements AND and OR.

Switch 18 of the completeness of control represents a beating binary switch that has the potential of a logical zero or one.

The channel switch block 19 and the band switch block 21 are k elementary binary toggle switches.

The control unit 3 with its first outputs is connected to the inputs of the test generator 4, the second outputs to the first inputs of the demultiplexer 6, the first inputs of the multiplexer 5 and the second inputs of the second selector 17, the third outputs of the control unit 3 are connected to the first inputs of the first selector 7. Fourth and fifth the outputs of the control unit 3 are connected, respectively, with the first and second inputs of the signature analyzer 8, the third

the input of which is connected to the output of the two-input element I Yu, and the output to the input of the indicator 9. The group of the first outputs of the control unit 3 is connected

The number of inputs to be checked is digital.

1. The demultiplexer 6 with its second inputs is connected to the terminals for connecting the outputs of the tested digital equipment 1, and the outputs to the second inputs of the first selector 7. The first selector 7 is connected to the second input of the two-input element I 10, the first input of which is connected with the output of the two-input element OR 20, and the output with the third input of the signature analyzer 8. The indicator 9 is connected to the outputs of the signature analyzer 8. The second inputs of the first comparison unit 12 are connected to the output terminals of the sensor 11 the second readout zone, the second inputs of the second comparison unit 14 with the outputs of the set of 13 master sets of the final readout zone.

The outputs of the first comparison unit 12 and the second comparison unit 14 are connected respectively to the first and second inputs of the OR element block 15, the third inputs of which are connected to the outputs of the range switch unit 21, the outputs of the OR element block 15 are connected to the first inputs of the second selector 17. The output of the second the selector 17 is connected to the first input of the two-way element OR 20, the output of the switch 18 of the completeness of the control to the second input of the two-input element OR 20.

The device for controlling multichannel digital equipment operates depending on the modes as follows.

In the full control mode, the full control switch 18 is in the on position with a logical unit at its output. This unit through the element OR 20 will open the element AND 10. The operation starts with the generation of the initial state signal in the control block 3 (Fig. 2) by pressing the button 37. This signal resets the elements of the control block 3 and the signature analyzer 8. By pressing the button 30 from the output of the element 27 of the control unit 3, shift pulses are output to the input of the signature analyzer 8. At this time, the address of the word (1) is removed from the outputs of the control unit 3 and the first test is recorded in the test generator 4 . The first test from the generator 4 tests through the multiplexer 5, controlled by information from the outputs of the control unit (k), is fed to the inputs of the channel 2.1 of the tested equipment 1. Information from the outputs of the channel 2.1

through the demultiplexer 6, controlled by the same information from the outputs of the control unit 3, comes to the inputs of the first selector 7. As the shift pulses are counted by the counter 28 in the control unit 3, the signals from the decoder 29 (p) are alternately connected via the selector 7 to the outputs of the demultiplex 6 through the open element AND 10 to the input of the signature analyzer 8, and the information about the first test from the outputs of the channel .2.1 over the shifts is written into the register of the signature analyzer 8. After the passage of n pulses, one is added to the counter 34 in block 3 and The second address of the generator 38 of the control unit 3 is repeatedly and alternately connected via the demultiplexer 6 and the selector 7 information from the channel 2.1 outputs, etc., one test after another is output, including the last one, until the overflow pulse from the counter 34 in the control block 3 will not change the state of the counter 35. From this moment on, the information from the second outputs of the control block 3 connects through the multiplexer 5 tests to the second channel of the equipment, and through demultiplexer 6 - the outputs of the second channel to the selections torus 7, etc.

After all the channels are connected in series, the overflow pulse from the counter 35 through the OR element 33 stops the arrival of the shift pulses from the generator 38 through the AND element 27 and the operation of the device stops. Indicator 9 records the value of the signature, which should be compared with the reference value. During one full cycle of operation, the counters 28, 34, 35 of the control unit 3 alternately connect the inputs of the channels 2.1-2.k to the test generator 4, and the outputs of these channels to the selector 7. In each channel

BUT

implemented 2 tests. For example, if hardware 1 is

The ROM is then set to 2 addresses, and at the moment when each test is submitted using the information selector 7, the read numbers from the outputs of each channel are alternately outputted to the input of the signature analyzer 8 and the shift pulses from the control unit 3 are recorded in the shift register of the signature analyzer 8.

In the second mode, the operation of the device, when the test program of the previously selected channels is analyzed, the output of the switch 18 for the completeness of the control is the logical zero. Block 19 of the channel switches on the part of its outputs corresponding to the disconnected channels, gives logical zeros, and on the outputs corresponding to the connected channels, logical units. On all outputs of the block 21 of the range switches there are logical units, i.e. on all the corresponding inputs of the block of elements And 16 also logical units.

Operation in this mode is characterized in that the potential at the first input of the AND 10 element is equal to one only when monitoring the connected channels and is equal to zero for the disconnected channels. This potential is outputted at the output of the selector 17 when the control unit 3 is operating. The analyzed information from the output of the first selector 7 is passed to the entry in the signature analyzer 8 through the element AND 10 only if there is a logical unit at its input connected to the output of the element OR 20, i.e. in those channels 2.1, which are connected with the help of a block of 19 channel switches to the control.

In the third mode of operation, it is possible not to control not only some channels completely, but also to maintain limited control on individual test words for each channel. In this mode, the output of the switch 18 full control zero. On those outputs of the block of 21 range switches that correspond to channels operating in a limited range of checks, there should be zeros, on the others, units. The selection of test ranges is carried out by blocks 11-14. The value of the range is determined by the number S of the high bits of the counter 34 in the control block 3 (S 1).

Out of the total 1 bits of the counter 34, in the control block 3, the S bits are assigned to ensure the selection of the numbers of the initial and final information transfer zones. Let, for example, 1 8, i.e. the number of bits of the counter 34 is 8, and the number of addresses assigned from the control unit 3 to the equipment 1 (for example, a ROM) is 2,256; let S 3 and since 5 3 then1 outputs of the sixth, seventh

five

0

five

five

0

five

0

and the eighth bits of the counter 34 are connected to the inputs of the comparison blocks 12 and 14. At the same time, from S outputs of counter 34, 2 8 numbers of eight memory zones (hardware 1), each of which contains 2 32 addresses, are fed to the inputs of blocks 12 and 14 of the comparison. In the event that it is necessary to begin the control of the apparatus 1, for example, from the third zone, the code 110 is dialed on the unit 11 of the setters.

At that moment of time, when the code 00000110 will be recorded in the counter 34, i.e. after 96 clocks from the start of the generator 38, the number specified on block 12 from block 11 of the setters and coming from counter 34 will be compared. The comparison signal will flow to block 15 of the OR elements and through blocks 16-18 to the AND 10 element, allowing recording control information.

During the whole time, starting from 96 to 128, the clock of the generator 38, i.e. when hardware 1 is set from 96 to 128 addresses, hardware atura 1 will be monitored. After writing the number 00000001 to counter 34, the enable signal Q from the output of block 12 is removed and the monitoring of equipment 1 is stopped.

The set of blocks 13 and 14 works similarly, while on block 13 any number of the zone of monitored addresses can also be dialed. The presence of blocks 11, 12 and 13, 14 in the device at the same time is due to the fact that in a number of cases it is necessary to control for one cycle the addresses located in two zones, for example, addresses from 120 to 140. At block 11, the code 000000110 is dialed, and in block 13, the code is 00000001, and the monitoring is performed in the third and fourth zones, which allows to override with control the entire memory field of the apparatus 1.

If control of one zone, for example a third, is necessary, then an identical code 00000011 is dialed on blocks 11 and 13.

The control unit 3 operates as follows.

By pressing the button 37, the triggers 23 and 26, the counters 28, 34 and 35 are set to 5, the initial state, and the output signal, Ex, goes to the initial state setting in the signature analyzer 8. By pressing

buttons 30 on trigger 31. a positive differential is generated, which is transformed on shaper 32 into a single start pulse of the required duration, which sets its unit on 1K flip-flop 23. On its negative front, OR 22 triggers on the trailing edge.

The continuous pulse sequence from the generator 38 passes through the open element AND 24, but the feather pulse of this sequence can be distorted in duration (shortened), and therefore cannot be used for shifts.

To eliminate it, the elements OR 25, the 1K-trigger 26 and the AND 27 element are introduced. The first pulse of the sequence does not pass through the AND 27 element, but merely cocks the 1K-trigger 26 into a single state on the falling edge, preparing the And 27 element to pass

3

connected with its first output outputs - with the first inputs of the multiplexer and the demultiplexer, the third outputs - with the first inputs of the first selector, the fourth and fifth outputs - with the first and second inputs of the signature analyzer, the second inputs of the multiplexer are connected to the outputs of the test generator, the multiplexer outputs with corresponding terminals for connecting the inputs of the tested digital equipment, the second inputs of the demultiplexer are connected to the corresponding terminals for connecting the codes of the tested digital equipment, demultiplexer outputs - with second inputs

the first selector, characterized in that, in order to expand the functionality of the device, a block of initial zone transmitters and a block of

Quantization of the second undistorted pulse, 25 ticks of the final reading zone, which can be used for shifts in the signature analyzer 8

The shift pulses arrive at three serially connected counters 28, 3A, 35. Counter 28 and decoder 29 on the n outputs provide alternate connection of the outputs of each of the k sanals through the first selector 7 and element 10 to the analyzer 8. Counter 34 for 1 binary digits An address counter is used to select the next of 2 tests from the 4 test generator. The upper bits of the counter 34, labeled S, are used to select the analyzed area in blocks 12 and 14 of the comparison.

Counter 35 with decoder 36 is designed to connect to analyzer 8 via multiplexer 5 and demultiplexer 6 of the terminals of the next of k channels. The overflow pulse of the last counter 35 through the element OR 33 resets the flip-flops 23 and 26 to the zero state and interrupts the shift pulses. Elements 22 and 25 provide triggers 23 and 26 on the trailing edge of the overflow pulse.

Claims (1)

Invention Formula A device for controlling multichannel digital equipment, comprising a first comparison unit, a range switch unit, a control unit five 0 five 0 five swarm comparison unit, channel switch unit, OR element unit, AND element unit, second selector, control completeness switch, two-input element AND, two-input element OR, the first inputs of the first and second comparison blocks are connected to the corresponding first outputs of the control unit, the second inputs of the blocks Comparison - respectively with the outputs of the setpoint adjusters of the inclined reading area and the setting units of the end reading area, the outputs of the first and second comparison units connect, respectively, with the first and second inputs the OR block, whose third inputs are connected to the outputs of the range switch block, the outputs to the first inputs of the AND block, the second inputs of the AND block are connected to the outputs of the channel switch block, the outputs to the first inputs of the second selector, the second inputs of which connected to the second outputs of the control unit, the output to the first input of the two-input OR element, the second input of which is connected to the output of the full control switch, the output to the first input of the two-input element And, the second input of the two-input element I is connected to the output of the first selector, the output is connected to the third input of the signature analyzer, the output of which is connected to the input of the indicator. DGH. FIG. five FIG. 6