SU1381598A1 - Buffer storage device - Google Patents

Abstract

The invention relates to storage devices and can be used as a buffer storage device for connecting a computer to the test object in debugging and diagnosing digital equipment. The aim of the invention is to extend the functionality by operating in the generation mode of test codes. The device comprises an input data conversion unit 1, a memory unit 3, a bus driver 5 and an output data conversion unit 6. The device operates in four modes: write, generate, register, read. 2 silt, 1 tab.

Description

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The invention relates to storage devices and can be used as a buffer storage device for connecting a computer to the test object in debugging and diagnosing digital equipment.

The purpose of the invention is to extend the functionality by operating in the test code generation mode.

FIG. 1 is given the structure diagram of the device; in fig. 2 - timing charts of the device.

The device comprises an input data conversion unit 1, a coding unit 2, a memory block 3, a decoding unit 4, a bus driver 5 and an output data conversion unit 6.

The device operates in four modes: write, generate, register, read.

In the process of diagnosing digital equipment, the proposed device receives test sets from a computer and places this information in memory block 3 (recording mode). In the Generation mode, test sets are read from memory block 3 and transmitted to the input of the test object. The reactions of the test object are accepted into the same device operating in the registration mode, which then, in the “Reading” mode, transmits this information to the computer. Information is exchanged with a computer in a sequential code, and with a test object in a parallel code. At the same time, the parallel code width (the number of input / output channels), as well as the corresponding data reception / transmission frequencies in the device and the capacity of memory block 3 per channel, can take one of four values (see table .). The table indicates: n - the size of the memory block 3, block 1 and block 6; / - speed of memory block 3: words in memory block 3.

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In the recording mode, test kits through the local shaper 5 from the first input / output of the device are recorded sequentially by shifting block 1, starting with its youngest bit. The control of the driver shaper 5 is performed by means of a control signal of 3 p / ch, arriving at its first input. The shift mode of block 1 is provided with a four-bit control code. in 1111, arriving at its control input. Promotion1381598

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The information on unit 1 is clocked by the SI I / O clock signal arriving at its sync input. From the second output (senior bit) of block 1, the data is bit-wise fed through the bus driver 5 to the second input / output of the device. At the same time, it is possible to connect other similar devices with the aim of increasing the size of the test sets (the second input-output / -th device is connected to the first input / output of the ((+1) -th device). O / O, VK and addresses A are shown in Fig. 2a.

In the "Generate test sets and corresponding check bits" mode, they are read out from memory block 3 under the influence of signals Zp / cht 1, and addresses A On the positive edge of the clock signal VC fed to the synchronous input of block 6, the read information is written to the specified register. From the output of block 6, the data is transmitted to the decoder 4, where they are monitored. Detection of a double error causes the formation of a signal at the first output of the decoding unit 4 connected to the control output of the device. When a single error occurs, the wrong bit is inverted, and the corrected test set arrives at the first information input of block 6. If no errors are detected, the test set goes to block 6 without changes. The control of block 6 carries the Control Out signal, which is fed to its control input. The data is recorded and promoted in block 6 by the sync signal of the SI I / O input to its sync input. Timing diagrams of SI signals I / O, VC, Ex. and addresses A are shown in FIG. 26

If the signal latch. has a constant value of "1, then in each measure

0 synchronization in block 6 is entered one test set, which in the same cycle with the maximum frequency / is transmitted to the information output of the device on n channels. If the signal latch. In one cycle it is equal to "1, and in the second one -" O, then in block 6, in the first cycle (Ex. Out. 1), two test sets are recorded with frequency / at the same time: one into bits with even numbers, the other with odd numbers . In the same cycle, the test set, placed in even-numbered bits, arrives at the information output of the device. In the next cycle (Control Out. 0) in block 6, data is shifted to the left, as a result of which the test set of bits with odd numbers is moved to bits with even numbers and is also transmitted to the information output of the device. Thus, Yuma, data transmission is carried out with a frequency of 2 / p / 2 even-numbered channels.

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If the signal latch. in one cycle it is equal to "1, and in three. nos the following." O, then in block 6 in the first cycle (Ex. Out. 1) with the frequency / are underused simultaneously four test sets. Data transfer to the information output of the device is carried out with a frequency of 4 / but n / 4 channels with multiples of 4.

If the signal latch. in one cycle it is equal to "1, and in seven consecutive" O, then in block 6 in the first cycle (Ex. Out. 1) with the frequency / are recorded simultaneously eight test sets. Data transfer to the information output of the device is carried out at a frequency of 8 / on p / 8 channels with no. Multiples of 8.

In the registration mode, the response of the test object comes to the first information input of unit 1 connected to the information input of the device. The control of block 1 is carried out using a 4-bit Inrush Code supplied to its control input. The recording and advancement of the data of the block I is performed on the sync signal of the SI in / out (see Fig. 2c). If the code Unr. In (O 3) 0000, then the filling of the block 1 takes place for 1 clock with the maximum frequency /.

If the code Exec. (O 3) 0100, then the filling of block 1 occurs in 2 cycles. In the first cycle, the input word is written in n / 2 bits with even numbers. In the second cycle, the nerve word is shifted to bits with odd numbers, and at the same time the second word is written into bit |) 1 with even numbers. LAAX. Total response rate 2 /.

If the code Exec. (O 3) 0100, then the filling of the block is 1 rd (X 1 digit per 4 clock cycles. In the first clock cycle, the input word is undershot in l / 4 bits with numbers that are multiples of 4. In the next three clock cycles, the right word is shifted from the previous clock cycles , and simultaneous recording of BHOBIJ of incoming words in bits with multiples of 4. The maximum frequency of the input response rate 4 /.

If the code Exec. (O-3) 01 I I, then block 1 is filled in 8 cycles, and the responses are received in n / 8 bits from the number multiples of 8, with a maximum frequency of 8 /.

In the Read mode, the response and the corresponding check bits are read from block 3 of the memory and go to block 6. At the same time, the block 3 parameters m works in the same way as in the Generate.

From block 6, the responses are transmitted step by step by Sdtvig, to the output of its low-order bit, connected to the third input of the local driver 5. The bus driver 5 broadcasts responses to its first input / output, the first input / output of the device. The mode of block 6 is determined by the value of the control signal of Ex. Record and promote

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Data arriving at the second input / output of the device is transmitted via the bus driver 5 to the second information input of block 6. As a result, the information received goes through block 6 and through the bus driver 5 enters the first input / output of the device. 0 With this. M it is possible to connect other similar devices in order to increase the response rate (the second input / output / -TH device is connected to the first input / output (/ -f-l) -ro device).

Input data conversion block I

can be implemented, for example, on the elements of the tina “Two-input register K531 IR20. In this case, the synchronous inputs of the elements are combined and fed to the synchronous input of block 1, and their first information inputs are connected to the first information input of block I. The second information input of each subsequent bit is connected to the output of the previous bit, which is the first output of block 1. The second information input the younger bit is fed to the second information input of block 1, and the high bit output to the second output of block 1. The control inputs of the elements are connected to the control input of block 1.

The bus driver 5 can be built on buffer elements with three states of the type K155 LP8 and an inverter. In this case, the output of the first element connected to the information input of the second element and the output of the third element connected to the information input of the fourth element are respectively the first and second input / output of the P1INNY shaper 5. The information inputs of the first and third elements are respectively - 0, by the third and second inputs of the bus driver 5, and the outputs of the second and fourth elements, respectively, by its first and second outputs. The control inputs of the second and third elements are connected to the first input of the P1inny form — 5 bodies 5, as well as the input of the inverter, the output of which is fed to the controls, 1) The first inputs of the first and fourth elements.

Formula.la invention

0 Buffer storage device, containing a storage unit, informational inputs of which are connected to the outputs of parallel data of the input data conversion unit, inputs of parallel data (which are informational inputs of the device, outputs of the storage unit of output data, B111INVES of parallel data of which in 0

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The information outputs of the device, the address inputs and the input of the memory block mode are the corresponding inputs of the device, the recording input of the input data conversion unit and the output data conversion unit are the corresponding inputs of the device, characterized in that, in order to extend the functionality of the device by work in test generation mode

The output data conversion unit, the second information input and the second information output of the women's driver are connected respectively to the serial data output and to the serial data input of the input data conversion unit whose sync input is connected to the sync input of the output data conversion unit and is the sync input of the device controlling input tire

codes, it contains a local shaper; the first shaper is connected to the mode input; the first information input and the first memory module, the first and second inputs and output of which are connected to the vegetable shaper, are respectively to the output of the serial and second data inputs and to the serial data input by the device outputs.

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Claims (1)

Claim A buffer memory device containing a memory unit, the information inputs of which are connected to the parallel data outputs of the input data conversion unit, the parallel data inputs of which are information inputs of the device, the memory block outputs are connected to the parallel data inputs of the output data conversion unit, whose parallel data outputs are information the outputs of the device, the address inputs and the input of the memory block mode are the corresponding inputs of the device, the recording input of the block the input data conversion and the output data conversion unit are the corresponding inputs of the device, characterized in that, in order to expand the functionality of the device by operating in the test code generation mode, it contains a bus driver, the first information input and the first information output of which connected respectively to the serial data output and to the serial data input of the output data conversion unit, the second information input and the second information output the bus driver path is connected respectively to the serial data output and to the serial data input of the input data conversion unit, the sync input of which is connected to the sync input of the output data conversion unit and is the device sync input, the control input of the bus driver is connected to the mode block memory input, the first and second inputs and outputs bus driver are the first and second information inputs of the outputs of the device. _d 12 3 16 17 18 19 32 33 GC 35 SIW / O _Π_ΓΊ_Π_ · · · _Γί_Π_η_Π_ * · 1Г1_П_ГЪЛ_ VK g G ΧΞΞΞ recording mode g ^- X SI input / output_A 8K A At Pr. out g ΞΧ SIWI / vih. And in pr. g SIW / you. R ~ ΞΧ At pr. Generation mode FIG. 2 o ΓΊ _______ SI8x! 6th _j si lx! would x ΐ -------- 1 ________ ΐ -------- 1ΐ— BK J I G A ~~ xX SI bx / out Bk A rzx Retin Registration SI 8x / 8b / x Bk 12 3 16 Π 18 19 32 33 3k 35 _Π_Π__Π_ · · · _ΓΊ_Π_Π_Π_ · · · _ΓΊ_ΓΊ_Π_Π_ I ----------------------------------------- A Control bykh. * * * * ^β 1 Retin reading 2 δ