SU1619326A1 - Device for receiving discrete information - Google Patents

Abstract

The invention relates to telemechanics and can be used DLR transmission of digital information over long lines of communication. The purpose of the invention is to increase the reliability of the received information. The device contains 4, 7 shift registers, synchronizer 5, pulse shaper B, decoders 8, 9, 11, 19, frequency divider 10, major element 12, RS flip-flop 13, multiplexers 14-16, memory blocks 17, 22, counter 18, element AND 20, element OR 21. The device allows the recipient of information at the same time as issuing information to report a failure for each bit of information output. 8 il.

Description

(/}

WITH

OE

I

figure 1

The invention relates to telemechanics and can be used to transmit digital information over long lines of communication.

The purpose of the invention is to increase the credibility of the received information.

1 shows a functional diagram of the device; figure 2 - the timing diagram of the device; FIG. 3 is a timing diagram of the formation of recording pulses; Fig. 4 is a diagram of the implementation of the majority element in the form of a one-bit combinational adder of three numbers; FIG. 3 is a diagram of the implementation of the third decoder in the form of a logical element 2-2I-2ShCHSH-NOT; figure 6 - scheme of implementation of the driver pulses which consists of two two-input elements And the frequency divider pulses into three, made on two 1, K-triggers and one three-input element And; Fig. 7 illustrates the implementation of the first decoder, the decoder of the transmission start code, which is performed on a one-bit combinational adder with as many numbers as the bits contain the transmission start code; in addition, the second decoder contains the AND element, which, based on the binary state analysis the code at the outputs of the adder generates a signal of the convolution of the code of the beginning of the transfer; FIG. 8 is a diagram of the implementation of the second decoder (code decoder) of the Barker, which is performed on a one-bit combinational adder with seven numbers and two three-input elements I.

The device contains (figure 1) input 1, the first 2 and second 3 outputs, the first shift register 4, the synchronizer 5, the pulse shaper 6, the second shift register 7, the first decoder 8, the second decoder 9, the frequency divider (pulses) 10, the third decoder 11, majority element 12, RS trigger 13, first multiplexer 14, second multiplexer 15, third multiplexer 16, first memory block 17, counter 18, fourth decoder 19, AND element 20, OR element 21, second memory block 22. Figure 2 shows the transmission start code 23, convolution of the transfer start code 24, Barker seven-bit codes, convolution 26 of the Bprker seven-bit codes; FIG. 3 shows: a triple pulse frequency 27, information bits 28 in a line.

ten

five

0

five

thirty

35

40

45

50

55

communication, information bits 29, recorded in the first shift register 4, recording pulses 30 at the output of the imaging unit 6 recording pulses.

The device works as follows.

Input 1 receives an array of information in the form of consecutive codes: code 23 for the start of transmission and seven-bit codes 25 Barker, which encrypt each bit of information. Information units are encrypted into direct Barker codes 1110010, zeros in inversion of Barker codes are 0001101. Information 28 is fed to input 1, then sequentially written to the first shift register 4 by an n-fold pulse frequency, where is an odd integer coming from the synchronizer output five.

The timing diagram of the formation of the write pulses in FIG. 3 is shown at.

Recorded information 30 from the four outputs of the high bits of the six-bit register 4 shift moves to the inputs of the decoder 11. At the moment when the outputs of the first two high bits of the register 4 have one logical voltage level, and the outputs of the two subsequent bits - the second logical a level, a signal is generated at its output, which synchronizes the shaper of 6 write pulses so that the write pulses 30 are formed in the middle zone of the information, which occupies one third of the discharge duration.

The device carries out an integral reception of information, the major element 12 is used for this two out of three, which analyzes the level of voltage of each bit of information in three zones of duration, if at least two of the three bits have the same logical a level, a corresponding level is formed at the output of the majority element 12, i.e. Majority element 12 corrects a distorted information bit if it is distorted by the level in any zone of the information bit, but no more than one third of the length of the information bit. Distortion of the information bit occurs both in the communication link, as a result of interference, and when writing to the shift register 4 because of the occurrence

51 f 1

asynchronous frequencies of the transmitter information and the synchronizer 5 in the device. This discrepancy is within the double tolerance of one frequency rating, for example, f 4 fKOM + uf is the frequency of the transmitting part, NOLL - & f the frequency of the receiving part. The frequency difference is f-f2 fHoM + & f-f40A ,.

Information bits from the output of the majority element 12 are fed to the input of the second shift register 7 and are recorded successively by write pulses 30 output from the driver 6. Information from the bits of the second shift register 7 is fed in parallel to the inputs of the decoder 8, the transmission start code and the decoder 9 Barker code. At the output of the decoder 8, a convolution 24 of the start of transmission code is formed, which is fed to the setup input of the RS flip-flop 13, the unit output of which is stored at the time of reception of the entire information array. Then, from the outputs of the shift register 7, the seven-bit Barker codes 25 are received and to the inputs of the decoder 9, the outputs of which form convolutions of 26, respectively, ones or zeros. The convolutions of the units arrive at the information input of the first memory block 17. A convolution of 26 ones and zeros from the descramble outputs ;. - torus 9 is fed to the inputs of the OR element 21, the installation input of the pulse frequency divider 10 is given a signal 24 from the output of the decoder 8 of the transmission start code. The convolution signals 26 from the output of the element OR 21 as the enabling signal arrive at the first input of the element 20 and as a message about a failure in the seven-digit Barker codes arrive at the information input of the second block 22. If the seven-digit codes of the Barker 25 are distorted in no more than one of seven bits, convolution signal 26 is recorded in block 22 as a logical unit, if the Barker code is distorted in more than one bit, convolution signal 26 is not present, and logic level zero is recorded in memory block 22. Divider No. pulse frequency divides the frequency of the pulses 30 recording seven. The installation input of the pulse frequency divider 10 is supplied with a convolution signal 24 of the transmission start code from the output of the decoder 8 of the transmission start code, to the counting input of the frequency divider 10 im0

: 3266

pulses received pulses 30 records from the output of the imager 6 pulseson. records The divided frequency of the pulses from the output of the divider 10 pulse frequency goes to the second input of the element AND 20. When there are convolution signals of units and convolutions of zeros at the first input of the element AND 20, the output of the element And 20, pulses are formed to record the decrypted information in block 17. Pulses for recording decrypted information generated by the output element And 20, through the multiplexer 16

5 are fed to the sync input of the memory block 17.

The logic level at the output of the RS flip-flop 13 during the reception of an array of information allows writing to blocks

0 17 and 22 of the memory and passes to the outputs of the multiplexers 14-16 internal sync signals. Pulses from the output of the pulse frequency divider 10 are fed to the first information input of the multiplexer 15, from the last output to the counting input of the counter 18 and the clock input of the second memory block 22. From the output of the decoder 8, the convolution signal 24 of the code for the start of transmission through

Qn / Liplexer 14 arrives at the installation input of the counter 18. Codes generated at the outputs of the counter 18 arrive at the address inputs of the memory blocks 17 and 22. At the end of receiving an array of information, the specific value of the counter code 18 at the output of the decoder 19 generates a signal that flushes the RS flip-flop 13. At the RS flip-flop output, an opposite logic level is set, which switches the memory block 17 and 22 from the write mode to the reading the recorded information and passes to the outputs of the multiplexers 14-16 external signals of synchronization, coming through the device inputs to the second inputs of the multiplexers 15 and 16 and the first input of the multiplexer 14.

From the output of the memory block 17, the information output is read out, and from the output of the memory block 22, the error message is displayed in each bit of information output.

In the device, the entire array of decrypted information is written to memory block 17. The convolution signals of the unit, generated at the output of the Barker 9 code decoder, are fed to the information input of the memory block 17 in quality 5

units of the decrypted information, and the absence of a convolution of the unit - as zero information. However, in the device, both the units and the zeros of the information are recorded in the memory unit 17 only in the presence of a corresponding convolution signal. If at the time of recording at this address a convolution of zero or a convolution of a unit is absent, then the recording in memory block 17 is not performed, but

The information from the previous session is received. In the memory block 22, a failure message is recorded for each section of output information. At the end of the reception of the decrypted information, the information is output to the output of the device, while simultaneously generating error messages for each bit of information output. This makes it possible for the recipient of information to more efficiently use the information received and, if necessary, correct it. This is an increase in the reliability of the information provided.

Claims (1)

Invention Formula A device for receiving discrete information containing the first shift register, whose information input is the information input of the device, the first and second outputs of the first shift register are connected to the inputs of the majority element, the output of which is connected to the information input of the second shift register, whose outputs are connected to the corresponding information inputs the first and second decoders synchronizer, the output of which is connected to the first input of the pulse shaper and to the control input of the first register but shift, the second and third outputs of which pogo connected to the inputs of the third decoder, the output of which is connected to the second input of the pulse shaper, the output of which is connected to the first input of the frequency divider and control five Q , five five 0 Leading inputs of the second register, first and second decoders, the output of the first decoder is connected to the first input of the trigger and to the second input of the frequency divider, the output of which is connected to the first input of the And element, the first and second outputs of the second decoder are connected to the same inputs of the OR element, the counter, the outputs of which are connected to the corresponding inputs of the fourth decoder, the output of which is connected to the second trigger input, characterized in that, in order to increase the reliability of the received information, you enter The first, second and third multiplexers, the first and second memory blocks, the first input of the first multiplexer and the combined first inputs of the second and third multiplexers are the first and second control inputs of the device, respectively, the second inputs of the first, second and third multiplexers are connected respectively to the output the first details of the encoder, to the output of the frequency divider and to the output of the And element, the output of the trigger is connected to the first control inputs of the first and second memory blocks, to the third inputs of the first, second and third ultiplexers is the output of the device, the output of the third multiplexer is connected to the second control input of the first memory block, the output of which is the first information output of the device, the output of the second multiplexer is connected to the first input of the counter and the second control input of the second memory block, output the first multiplexer is connected to the second counter input, the outputs of which are connected to the corresponding address inputs of the first and second memory blocks, the first output of the second decoder is connected to the information The first input of the memory block, the output of the OR element is connected to the second input of the AND element and to the information input of the second memory block. 41 Li Fm.2 FIG. H Fy 1l 1l inWi B about ie -I  TO L. and Ј rL 0 four U s jwo 9Zt6l9l from 4 FIG. eight