SU1372366A1 - Device for detecting and correcting errors - Google Patents

Abstract

The invention relates to computing technology, in particular, to devices for detecting and correcting errors in memory and computer devices, and can be applied to memory devices with sequential access and high speed. The aim of the invention is to improve the accuracy of error detection and correction by using a Fire code. The device contains an error detection block 1, an error code memory block 2, an error address memory block 3, a buffer memory block 4, a correction block 5, a switch 6, a serial code to parallel converter 7, an 8 F block

Description

WITH/)

address switching, a counter 9 clock pulses, a switching signal switching unit 10, an OR element 11 and a comparison block 12. The goal is achieved due to the fact that the device provides error detection of up to twelve bits and error correction of up to six bits in the information read by the external drive and received at input 13 in the sequential code. In block 4, the information is recorded by a parallel code. Block 1 implements decoding using the Fire code and generates on

on its outputs, the signal of the presence or absence of an error, a signal of a corrected or uncorrectable error, transmits to block 2 an error packet code and to block 3 data for determining the number of the first error byte and the first error bit in this byte. Block 12 compares the numbers of erroneous bytes with the current reading address from block A and their three coincidences generates a signal that includes correction of the read information in block 5. Table 1, 6 Il.

one

The invention relates to computing, in particular, to devices for detecting and correcting errors in memory devices, and can be used in memory devices with sequential access and improved speed.

The aim of the invention is to improve the accuracy of error detection and correction by using a Fire code.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 through 6 are functional diagrams of the most preferred embodiments, respectively, of the detection unit opshbok, address selection unit, access signal switching unit, error address memory unit and switch.

The device contains (Fig. 1) an error code memory block 2, an error detection block 1, an error address memory block 3, a buffer memory block 4, a correlation block 5, a switch 6, a serial code converter 7 into a parallel address select block 8 counter 9, inverter shaper 10, element OR 11, block 12 comparison. FIG. 1 denotes information input 13, output 14 recognizes the presence of an error, output 15 indicates an uncorrectable error, information outputs 16, mode control input 17, access input 18, address inputs 19. first 20 and second

21 synchronous inputs, input 22 of the initial installation of the device. The device also contains a synchronization driver 23 comprising an element NOT 24, a generator of 25 pulses, a trigger 26 and element 27.

The error detection unit 1 contains (FIG. 2) the registers 28-32, the overhead signals from the D-flip-flops 33 and the parity generator 34, the counters 35-38, the blocks 39 and 40 of the comparison, the elements AND 41-47 and OR-48 -50, elements 51 and 52, element OR 53 and triggers 54 and 55.

Unit 8 address selection contains (fig.Z) counter 56, the switch 57 and the element And 58.

The switching signal switching unit 10 comprises (FIG. 4) an AND element 59, a switch 60, a delay element 61 and a call signal generator 62. FIG. 5 and 6 shows elements 63-67.

As block 2 of the error code memory and block 3 of the error address memory, for example, blocks of permanent memory can be used. The table shows a fragment of the truth table of the work of block 3.

The device works as follows.

Before receiving information from an external storage device (not shown) at input 22, the block 8 (Fig. 1), the counter and the block 1 are zeroed out. The information to the device comes from

external accumulator at input 13 in the serial code to converter 7 and simultaneously into block 1. Information is received via synchronization CC1 inputted at input 20. The frequency of receipt of CC1 is determined by the frequency of operation of the external storage device.

Converter 7 generates parallel words (for example, bytes), information about which is fed to the inputs of block 4. At the same time, input 17 to block A receives a log signal. O (write), block 10 generates a reference pulse for each byte of information. Unit 8, in accordance with the information received from the counters 9, sequentially searches the addresses of unit 4.

Block 1 of this particular case implements the procedure of a decoder with the example of the Oai ipa code with the evolving polynomial P / X / (X + 1) (X + + X + 1) (X + X + i). This code allows you to adjust the size of a bit up to six bits and match errors up to twelve bits. The code length is 1155 bits with eighteen bits per bit.

Unit 1 is responsible for the decal of the received information, resulting in the following sip-ipl: output 14 signals log. 1 1 log O correspond to the presence or absence of an error in the received information at the output of 15 signal log. 1 or log. O correspond to a corrected or necor; 5C): tirismma 1ib1; s; Block 2 receives the package code of the package, which is an alternation of ones and zeros in accordance with how the information is distorted (the size of this code is determined by the generator

BY

Number of the first erroneous bit in the 18th byte

On the basis of this sequence, the fifth from block 2 places the packet opshbok, incidentally:

12345 00000

6 7 8 9 10 12 13 14 15 16 + + + + + About 0.0 00

0

five

0

S

0

Fire's polynomial code and in this example is six; the signal that the detected error is localized is received by blocks 3 and 6; the data needed to determine the numbers of the byte bytes transmitted to block 3.

Thus, by the time the information is received, it is all placed in block 4, and after a certain number of ticks (for a given polynomial after 26 ticks) there is the necessary information to correct the error.

Information transfer to the outputs 16 with simultaneous correction can, if necessary, be performed with a higher frequency, therefore the device provides the possibility of applying a second synchronization series to the input 21 in the presence of a signal of corrected error, for which the former 23 is used.

Pa og nonone information about the location of the error is formed) 1nPCH in block 1, block 3 generates: the number of the erroneous byte, the number of the first erroneous bit in the byte and the number of the next 6aviTa, since the error packet can capture two bytes. Pomer of the first error bit and HONiep of the first erroneous byte from block 3 together with the error packet from block 1 goes to block 2. In accordance with this, and on the outputs of block 2, I see two bytes on the outputs of block 2, which is distributed in a required manner . For example, if the error packet size is six, and the number of the first bit of the bit in the code information sequence is 142, then block 3 generates the following sequence;

10011

Binary code number of the second erroneous byte (for example, the 19th)

block 1

The following is CGD + + - the error code bit corresponding to the error bit in the code information sequence.

Block 3 contains information

about the error addresses in accordance with the table, in each cell of which the erroneous byte number and the corresponding first erroneous bit (bit) in this byte are indicated, depending on the contents of K ,, and K, respectively, counters 35-37 (figure 2) .

The filling of the memory of block 3 in accordance with the table is as follows.

Example. Let the contents of K, Kj, K ,, counters 35-37 be equal, respectively, 8,6,1. To obtain

The error correction procedure is started by sending a read signal (log. H) to input 17. The presence of inversion signals at the output of block 10 and addresses at output 19 through block 8 provide sampling from block 4 of data received at block 5 for correction.

measure of the wrong bit you need to create a system:

ix, - 8 modulo 11;

 6 modulo 15;

 1 modulo 7.

Using the original modules, we get: 11x15x7 1155 107x11x15 165x7, and

105x2xK, 1 modulo 11;

77x8xK, 1b5x2xK Then ix

1 modulo 15; 1 modulo 7

210xK + 616xKj + 330xKj modulo 1155. Substituted, we get:

ix 210-8 + 616.-6 + 330 1 in 1086 modulo 1155.

According to the number of the first erroneous byte 1086: 8 135, we find the number of the first erroneous bit in the byte: 8x0,76 6.

In addition, in each cycle, the address of the next byte arrives at block 12, the other inputs of which receive the addresses of the first and second erroneous bytes from block 3.

As long as the address of the read byte does not coincide with the numbers of erroneous bytes, information from block 4 is transmitted without change to outputs 16. If the address of the next byte reads out with the number of the erroneous byte, for example, on the eighteenth, block 12 generates a coincidence signal, and the data from the output of switch 6 is fed to block 5, in which the corrupted byte from block 4 is modulo-2 added to the 6 byte from the switch, in which the last three bits are an addition to the distortions. recited information. When reading from block 4, the next byte triggers block 12, and in block 5 comes through switch 6 a second additional bytes. All subsequent bytes from block 4 are transmitted to outputs 16 without change.

Thus, the information is corrected using the Fire code, which allows detecting errors of up to twelve bits and correcting errors up to six bits.

Claims (1)

Invention Formula A device for detecting and correcting errors, comprising an error detection block, a correction block, an error address memory block, an error code memory block, a switchboard and a buffer. the memory block, the write / read input of which is an input; the controls for the operation mode of the device whose information outputs are the inputs of the correction block, one of the information inputs of which is connected 1 with the output and the buffer memory block and the other information inputs of the correction block connected to the switch outputs, one of the information inputs of which are connected to the outputs of the error code block, one of the address inputs of which are connected to the outputs of the first group of the error detection block, the outputs of the second group of which are connected Enes with addressable entries of the memory block of addresses OECH, characterized in that, in order to improve the accuracy of detection and correction of errors by using the Fire code, an address selection block, a reverse signal conditioner, a serial code to parallel converter, a counter, an IIJIJI element and a comparison unit are entered, one of the inputs of which and one of the address inputs of the address selection block are address inputs of the device, the counter outputs are connected to the counting inputs of the selector addresses and one of the clock inputs of the reference signal generator, the outputs of which are connected respectively to the address inputs and the reference input of the buffer memory block, the write / read input of which One input with the start address of the address selection block and the first start input of the reference signal generator, the second start input of which is the input of the ycTpoiiCT output, the information inputs of the buffer memory block are connected to the outputs of the next converter: the new code to the parallel, whose information input and information input the error detection unit are combined and are the information input of the device, the first input of the 1SHI and the synchronization inputs of the counter, the address selection unit, the iBeeer and the converter via sequential code in parallel are combined and are the first synchronized input of the device, the second synchronized input of which is the second input of the OR element, the output of which is connected to the synchronization input of the error detection unit, the nepBbtfi output of which is connected to the control input of the switch and the address of the error address memory block The outputs of which are connected to other address inputs of the memory block of the code of the fault and other inputs of the comparison block, whose outputs are connected to other information inputs of the koshutator, the installation the inputs of the counter, the error detection unit and the address selection unit are combined and are the input of the initial installation of the device, the second and third outputs of the error detection unit are respectively the output of the sign of an error and the output of the sign of an uncorrectable error 13 Ofnn