RU1837363C - Self-testing memory device - Google Patents

Abstract

The invention relates to computer technology and can be used to create semiconductor memory devices with increased functional reliability. The aim of the invention is to increase the speed of the device. The memory device with autonomous control contains operational and permanent storage, a control unit, an encoding unit, a decoding unit, first and second switches, a multiplexer, first to third comparison units, a counter, first and second adders modulo two, from first to third registers , first to third elements I. 8 ill.

Description

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The invention relates to computer technology and can be used to create memory systems with enhanced functional reliability.

The aim of the invention is higher H1

e device performance.

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Figure 1 shows a structural diagram of the proposed storage device with autonomous control; figure 2 is a structure of a control circuit; in Fig. 3, a modulator two modulator; Fig. 4 is a diagram of a comparison unit; 5 is a diagram of a decoding unit; figure 6 - diagram of the counter; Fig. 7 is an example of constructing a test trice of matching codewords; on the

g8 - the algorithm of the device.

The device (Fig. 1) contains an operative drive 1, the inputs of the first group 2 of which are connected to the inputs of the first group of the first adder modulo two 3, the information inputs of the first group 4 and the second group 5 of drive 1 are connected respectively

Accordingly, with the outputs of the first 6 and second 7 switches, the inputs of the first group of switch 6 are connected to the inverse outputs of the first register 8 (the control input of the register is not shown), the inputs of the second group of switch 6 are connected to the inverse outputs of the second adder modulo two 9, the inputs of the second group which are connected with the outputs of the permanent drive 10, the inputs of the second group of the first adder modulo two 3, the first 11 and the second 12 elements And, the inputs of the first group of the second adder modulo two 9 are connected to the direct outputs of the first p register 8, the inputs of which are connected to the outputs of the encoding unit 13, the inputs connected to the information inputs 14 of the device. l

The outputs of the second group 15 of the operational drive 1 are connected to the information inputs of the first group of the multiplexer 16, the information inputs of the second group

which are connected to the outputs of the counter 17 and the inputs of the first group of the second switch 7. The control input of the multiplexer is connected to the control input of the device, and its outputs are connected to the address inputs of the constant drive 10, the first 18 and second 19 control inputs of the drive are connected respectively the second 20 and third 21 outputs of the control unit 22., the first input and the first output of which is connected respectively to the control input 23 and the output 24 of the device, the fourth output 25 of the block 22 is connected to the control input of the first switch b, the second the input 26 of the block - with the second output of the first block of comparison 27, the first inputs of which are connected to the information inputs of the second 28 and third 29 registers. The information inputs of the first and second groups of the first block of comparison 27 are connected respectively to the outputs of the first switch 6 and the outputs of the random access drive 1. The fifth 30 and sixth 31 outputs of the control unit 22 are connected respectively with the first and second inputs of the counter 17, seventh 32, eighth 33. ninth 34 and tenth 35 outputs of the block - with control inputs, respectively, of the second register 28, third register 29, permanent drive 10 and second switch 7, the outputs of registers 28 and 29 are connected respectively to the inputs of the first group of the first element And 11, the second unit of comparison 3.6 and the second element And 12, the third unit of comparison 37. The outputs of the elements And 11, 12 are connected to the inputs of the second group of units of comparison 36 and 37, respectively, the outputs connected to the inputs of the third element And 38, the output of which is connected to the third input 39 of the control unit 22, the control inputs of the first adder 3 and the decoding unit 40 are connected to the control input 23 of the device. The inputs of the decoding unit 40 are connected to the outputs of the first adder 3, the device also contains address inputs 41 connected to the address inputs of the drive 1, and information outputs 42 connected to the outputs of the decoding unit.

The control unit 22 (Fig. 2) is constructed on the basis of machine synthesis of the Miles machine in accordance with the purpose of the inputs and outputs of the unit and the device operation algorithm (see below) according to the known method. Block 22 consists of PLM 43, register 44, first 45 and second 46 permanent drives, Some inputs of PLM 43 are connected to inputs 23.26, 39 of block 22, Inputs 47.48.49 of PLM are with outputs of register 44, third input 50 PLM 43 through the element OR 51 is connected to the first

the input 23 of the block 22. The outputs 52, 53, 54, 55 of the PLM are connected to the inputs of the first 45 and second 46 permanent drives. The outputs of the accumulator 45 and the first output of the accumulator 46 are connected to the first tenth outputs of the control unit 22. Other outputs of the accumulator 46 are connected to the inputs of the register 44, the synchronization of which is carried out by known methods.

The adder 3 modulo two (Fig.Z) consists of adders 59 and valves 60.

Comparison unit. (Fig. 4) consists of adders modulo two 61 and valves 62.

5 Similarly, blocks 9, 36, 37 can be constructed.

The coding unit 13 consists of modulo two adders and calculates the verification code relationships

0 Hamming. The decoding unit 40 (Fig. 5) consists of a coding unit 63 similar to block 13, a syndrome calculation unit 64, an error location decoder 65, and error correction unit 66. The inputs of block 63 receive information (R) symbols with the output of block 3, and at the outputs of block 63, newly generated check bits of the code word, which are compared in block 64 (as in

4) with check bits coming from block 3. Correction block 66 is constructed in the same way as block 3.

Figure 6 shows a diagram of the counter 17, which may consist of actually

5 of a standard counter 67, first 68 and second 69 AND elements, OR element 70, trigger 71, delay element 72, generator 73.

Switches 6 and 7 can represent

0 are ordinary valves.

In Fig. 7, the numbers 74 of the matching code layers and the control bits 75 are indicated with 23 information and 5 control bits.

5 The device operates as follows (Fig. 8). When the power is turned on, the initial installation of all elements of the device occurs. In the recording cycle, information bits enter the inputs 14 into the block

0 13 encoding which generates r linear code check characters. Code word consisting of n characters (), through direct outputs of register 8, adder modulo two 9 and switch

5 b is recorded in the drive 1 by inputs 4. The recording is made at the address supplied to the inputs 41 of the drive by the signal at the control input 18 of drive 1. The signal at the output 20 of the control unit 22 is generated upon the arrival of a pulse

nor control input 23 of the device. Thus, the primary codeword is written to the drive 1. Then, a control reading of this word is performed on the outputs of drive 1; the operation is allowed by the signal at input 19 of drive 1, this signal comes from the output of block 21 at etching 22. Comparison unit 27 determines whether the recorded codeword matches the read word. The first one enters the codes of block 27 from the output of switch 6. There is no signal at the code word equality. Error at one of the outputs of block 27; at the same time, block 22 generates a Ready signal for output 24, which means that it is possible to process (write or read) the next code word.

If the read and written words he coincide at least in one bit, block 7 generates an Error signal, which is input to input 26 of control unit 22, and the sum modulo two of these code words is sent to the inputs of registers 28 and 29. 22 generates a signal. Record on output 20, signal Forward / Inverse - on output 25, signal for allowing information to be entered in register 28 - on output 32. As a result, an inverse code word is written to switch 4 at inputs 4 through switch O; the same word will go to the comparison block 27. Next, a check reading of the inverse code word is carried out and its j block 27 is compared with the written one. If there is no; ignal Error At the output of block 27 through switch 7 in drive 1 (for the same address), the value of the address of the matching word (all bits of which 0 correspond to 1) is written, which, when reading, will establish that the word was inverted - grounded in recording mode (the address code of this word is constantly at the outputs of the second group of switch 7). Then a Ready signal is generated.

Matching code words are recorded in the read-only memory 10 in the form of a verification matrix corresponding to a linear code (Hamming, for example). All rows of the matrix are linear code words, and the numbers of all code words are different.

If the error signal иб error is generated at the output of block 27, it is input to control unit 26; block 22 generates a signal at output 33, which permits writing information from block 27, to register 29, a signal at output 34, that allows reading the code word from drive 10 at the address generated by counter 17 when a signal is received at its input Start counter from output 31 block 22. Under the influence of these

of signals, the permanent drive 10 sequentially provides code words that are input to the inputs of the second group of elements 11, 12. These elements, as well as blocks 36 and 37, the element And 38 search for such a matching code word so that when writing to the defective cell of the drive 1 sums modulo two primary codewords with matching word no errors occurred. If such a matching word is found, then from the output of the And 38 element, a single signal is supplied to the input 32 of the block, under the influence of which the block 22 generates a Stop counter signal 17 at the output 30, a Write signal to the drive 1 at the output 20, and a signal at the output 25 , which allows recording the sum of the direct and matching code words, goes to switch 6 and then to the corresponding memory cell of drive 1.

If a matching codeword is not found, i.e. the counter went through all the addresses, then (according to Fig. 8), after receiving the address of the last matching codeword, the counter 17 will be set to zero. A processor or other external device (not shown in FIG.) Will detect the presence of an unrecoverable error. External signals establish a new memory access cycle.

In the information reading cycle, the symbols from the outputs 2 of the drive 1 go to the adder 3. In addition, from the outputs 15 of the drive 1 to the information inputs of the first group of the multiplexer 16, the number of the matching code word is received, which is the address of the constant drive 10. The output 34 of the block 22 is generated a signal allowing reading from the drive 10. The matching code word from the outputs of the drive 10 is fed to the inputs of the adder 3: it is bitwise added to the information code word read from the drive 1. At the same time, navlivaets original information word. If there is an error in this word that occurred between the last two calls to this cell, then such an error will be corrected by the decoding unit 40. At the device outputs 42 there will be an original information word without errors. After the time required to complete these operations, a Ready signal is generated.

Thus, the proposed device with autonomous control corrects the same number of errors in the information as in the known one. The verification matrices for generating matching codewords are identical in both devices. However, the duration of the recording cycle in the proposed device is less than in the known. Indeed, in the known device (prototype), the time required to write to the information storage device, taking into account the existing faults of the interrogation cell of the interrogated cell, consists of time periods determined:

the formation of the code word (primary) and its recording in the drive 1;

reading the primary code word from drive 1 and detecting inconsistent errors,

search for a matching codeword,

writing an inverse codeword to the accumulator 1 by reading the inverse codeword from the accumulator 1 and searching for the coordinated (with respect to the primary codeword) errors;

searching for a new matching codeword,

the formation of the final code word, taking into account agreed and inconsistent errors,

final record in the operational drive 1 of the code word, the formation of which is marked p.

In the proposed device, the maximum duration of the write cycle is reduced due to the fact that the matching codeword is generated once: after the location of the agreed and inconsistent errors in the primary codeword is established. In the proposed device, only consistent and inconsistent errors are detected in the code words read from the drive. The determination of the logical state of defective (failed) EFs in the drive cell is sufficient to form the final codeword. Due to this, the speed of the device is increased and, in addition, the hardware costs of implementing the redundant part of the device are reduced. The assessment shows that the speed of the proposed device is 15-20% higher than the speed.

Claims (1)

SUMMARY OF THE INVENTION A memory device with autonomous control, comprising an operational storage device, a control unit, an encoding unit, a decoding unit, first and second switches, a multiplexer, first to third comparison units, a read-only memory device, a counter, the first and second adders modulo two, from first to third registers, from first to third elements AND, and the inputs of the first group of the first adder modulo two and the first the comparison units are respectively combined and connected to the corresponding outputs of the first group of the random access memory, the outputs of the second group of which are connected to the information inputs of the first group of the multiplexer, the information inputs of the second group of which are connected to the outputs of the counter, the control inputs of the multiplexer, the first adder modulo two, the decoding unit and the first input of the control unit is combined and is the control input of the device, the control output of which is the first output of the control unit, the second and third outputs of which are connected respectively to the first and second control inputs of the random access drive, the address inputs of which are the address inputs of the device, the information inputs of the first group of the random drive and the information inputs of the second group of the first comparison unit are respectively combined and connected to the outputs of the first switch, the inputs the first group of which is connected to the corresponding inverse outputs of the first register, the direct outputs of which are respectively connected to the inputs of the first group of the second adder modulo two, the inputs of the second group of which and the inputs of the second group of the first adder modulo two, respectively, are combined and connected to the outputs of the constant drive, the address inputs of which are connected to the corresponding outputs of the multiplexer, the input of the first register is connected to the output of the encoding unit the inputs of which are the information inputs of a device whose information outputs are the outputs of a decoding unit, the information inputs of which are connected to the corresponding the moves of the first adder modulo two, the outputs of the second adder modulo two are connected to the corresponding inputs of the second group of the first switch, the control input of which is connected to the fourth output of the control unit, the fifth and sixth outputs of which are connected respectively to the first and second inputs of the counter, the seventh, the eighth and ninth outputs of the control unit are connected respectively to the control inputs of the second and third registers and a constant drive, the information inputs of the second and third registers are combined and connected to the first output of the first comparison unit, the second output of which is connected to the second input of the control unit, which, in order to increase the speed of the device due to the reduction of time losses in excess q (l, the tenth output of the control unit is connected with the control input of the second switch, the inputs of the first group of which are connected to the corresponding outputs of the detector, the inputs of the second group of the second switch / inputs are inputs of the logical 1 device, the outputs of the second switch are connected to the information Discount inputs in Ora-accumulator operative group, the first group of inputs of the first AND gate and the comparator orogo respectively combined and connected to the outputs vtoro0 of the first register, the inputs of the first group of the second AND element and the third comparison unit are respectively combined and connected to the outputs of the third register, the inputs of the second group of the first and second I elements are respectively combined and connected to the outputs of the constant drive, the outputs of the first and second elements AND are connected respectively to the inputs the second group of the second and third comparison blocks, the outputs of which are connected respectively to the inputs of the first and second groups of the third element And, the output of which is connected to the third input of the control unit occurrence. tpvS.j 0Ј & Ј # ЈЈ € gЈ tЈ SZ & tt 02 6Ј & S S9CAC81 From the breath. fa.3 42 & Ј / & 6 30 / rt / cfy . 3ff / f. wrote (X) ff # orff. / I b. jtor. Mff0afJi) fXt). J yficrfM v j 1 Jfew ff-0r 8: X & Jff - 2; IJE7 / 7. c / ffffct Xf / vof / fy / ra / TroMi / tfe 0 # / r. t / srrfwe h Yeshe estfffa / z vav. -f y / rr & we e / 70 # (/ f / s # &. Щ f / fffaqaaffo s / e / e synerp, | llg t / .t / & b0 & Јs7Ј Are / e 0О / & 0Ж. / 0 / rrffЈ // 0Csr u (jyes / ey) 1  Jff / ra