SU1370781A1 - Pulse counter - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in discrete information processing devices, in particular as noise-resistant counters, pulse distributors, decoders, and noise-resistant information coding devices. The aim of the invention is to expand the functionality. The goal is achieved through the introduction of the elements OR 13.1-13.4 and the elements 14.1-14.4 of unevenness, as well as new design features that make it possible to localize decryption errors. The drawing also shows: the first elements OR 1.1–1.5, triggers 2.1–2.5, elements NOT 3.1–3.5, first elements AND 4.1–4.5, second elements AND 5.1–5.5, second elements OR 6.1–6.3, adders (L

Description

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7.1-7.5, input bus 8, elements And 9.1-9.2 of the first group, elements And 10.1-10.3 of the second group, elements And 11.1-11.4 of the third group and elements 12.1-12.5 of the fourth group. The device provides localization of the decryption error in codewords. A joint failure or failure of the outputs of the adder and decoder is of little likelihood. 1 il.

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The invention relates to automation and computer technology and can be used in discrete information processing devices, in particular, as noise-resistant counters, decoder pulse distributors, and noise-resistant information coding devices.

The aim of the invention is to expand the functionality.

The goal is achieved by identifying new design features that provide the ability to localize the decryption error.

The drawing shows a five-bit pulse counter with a control number K equal to four.

The counter contains the first elements OR 1.1-1.5, the triggers 2.1-2.5, the elements NOT 3.1-3.5, the first elements I-4.1-4.5, the second elements AND 5 5.5, the second elements OR 6.1-6.3, adders 7.1-7.5, input bus 8, elements AND 9.1-9.2 of the first group, elements AND 10.1-10.3 of the second group, elements AND 11.1-11.4 of the third group, elements AND 12.1-12.5 of the fourth group, elements OR 13.1-13.4, elements 14.1-14.4 of unequalities.

The first groups of inputs of adders 7.1-7.5 are connected respectively to the direct and inverse outputs of flip-flops 2.1-2.5, the installation inputs to the unit of which are connected respectively to the outputs of the first elements AND 4.1-4.5, the inputs to the installation of zero triggers 2.1-2.5 are connected respectively to the outputs of the second elements And 5.1-5. The first inputs of the second elements AND 5.1–5.5 are connected respectively to the outputs of the first elements OR 1.1–5.5 and connected respectively to the inputs of the elements NOT 3.1–3.5, the outputs of which are connected respectively to the first inputs of the first elements AND 4.14.5, the outputs of the second elements 5.15. 4 are connected respectively with the first inputs of the second elements OR 6.1-6.3, with the second input of the first element AND 4.5 and are connected respectively with the second inputs of the second element I

cops And 5.2-5.5, the second inputs are first

elements AND 4.2-4.4 are connected respectively to the outputs of the second elements OR 6.1-6.3, the input bus 8 is connected to the second input of the first element AND 4.1, to the second input of the second

element AND 5.1 and the third inputs of the first elements AND 4.2-4.4, the first inputs of the first elements OR 1.1-1.5 are connected respectively to the direct outputs of the flip-flops 2.1-2.5, the second inputs of the first elements OR 1.1-1.5 are connected to the output of the adders 7.17 .5 corresponding to the control number To, the second group of inputs of adders 7.1-7.4 are connected respectively to the outputs of adders 7.2-7.5, the outputs of adder 7.1, corresponding to the numbers from zero to K-1st, are connected respectively to the second inputs of the second elements OR 6.3-6.1 and

with the third input of the first element AND 4.1, as well as with the first inputs of the elements AND 9.1-9.2 of the first group, the elements 10.1-10.3 of the second group and the elements 11.1-11.4 of the third group respectively, the direct output of the trigger 2.1 is connected to the inputs of the elements 12.1- 12.4, the direct output of the trigger 2.2 is connected to the inputs of the elements And 12.1-12.3, 12.5, 11.1-11.3, the direct output of the trigger-2.3 is connected to the inputs of the elements And 12.1-12.2, 12.4-12.5, 11..2, 11.4, 10.1, 10.2, the direct output of the trigger 2.4 is connected to the inputs of the elements And 12.1, 12.3-12.5, 11.1, 11.3, 11 .4, 10.1, 10.3, 9.1, the direct output of the trigger 2.5 is connected to the inputs of the elements And 12.2-12.5,

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Sections 2-11.4, 10.2, 10.3, 9.2, and the codes of the elements AND 9.1-9.2, 10.1-10.3, 11.1-11. A, 12.1-12.5 and zero output of the adder 7.1 are the outputs of the decoder and are connected respectively to the inputs of the elements OR 13.4 -13.1, the outputs of which are connected respectively to the second inputs of the elements 14.4-14.1 unequalities, the first inputs of which are connected respectively to the outputs of the adder 7.1, the corresponding numbers from first to fourth.

De-erification errors are localized as follows.

If, for example, the counter is in the state 01000, which corresponds to the number 1, then a single signal appears at the output of AND 9.1, which through the OR 13.4 element enters the second input of the unequality element 14.4. The first input of this element also receives a single signal from the first output of the adder 7.1. Since the signals at the inputs of this element coincide, therefore, at its output there is a zero signal. The outputs of the elements 14.1-14.3 also have a zero signal, since the inputs of these elements have zero signals. If a single signal disappears as a result of a failure or failure at the out of the And 9.1 element, then a zero signal appears at the second input of the inequality element 14.4.

37078 As a result of the signal mismatch at the inputs of element 14.4, the value is not equal

five

0

mistakes. If, as a result of a failure or failure in the described case, any other output of the decoder from another group, such as an output of an AND 10.1 element, is excited, then a single signal from this element will go to the second input of the unequality element 14.3 and an error signal will appear at the output of this element, which simultaneously indicates to the group of busbars of the decoder in which the error occurred.

Similarly, deciphering errors are located in other code combinations. A joint failure or failure of the outputs of the adder and decoder is of little likelihood.

Claims (1)

Invention Formula Pulse counter auth. St. No. I274I53, characterized in that, in order to expand its functionality, K elements of H and K elements of UNIMQUENCY are additionally introduced into it, the first input of the i-element of the UNIFORITY is connected to the output of the first-digit adder corresponding to the number i, the second input of the i-ro the UNCHARTERNESS element is connected to the output of the i-element of the OR element, whose inputs are connected to the outputs of the elements of the i-th group.