SU1274153A2 - Pulse counter - Google Patents

Description

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The invention relates to automation and computing technology and can be used in discrete information processing devices, in particular, as noise-resistant counters, pulse distributors, decoders and devices for noise-resistant information coding, and is an improvement of the known device according to the main author. St. No. 1077054.

The indicated counter has a high noise immunity, but does not have the ability to decipher the states of the counter.

The aim of the invention is to expand the functionality.

This goal is achieved through the introduction of new design features, ensuring the use of, and their decoding of the states of the pulse counter.

In the drawing, as an example, there is a five-pulse pulse counter with a control number k, equal to four, which is capable of decoding its state.

The device contains the first elements OR 1.1-1.5, the triggers 2.12 .5, the elements NOT 3.1-3.5, the first elements AND 4.1-4.5, the second elements AND 5.1-5.5, the second elements OR 6.16 .3, adders 7.1-7.5, input bus 8, elements And 9.1-9.2 of the first group, elements And 10.1-10.3 of the second group, elements And 11.1-11.4 of the third group, elements And 12.1-12.5 of the fourth group.

The first groups of inputs of adders 7.1-7.5 are connected respectively to the direct and inverse outputs of the trigger 2.1-2.5, the installation inputs to the unit of which are connected respectively to the output Miiq of the first elements AND 4.1-4.5, the installation inputs to the zero of the trigger 2.1-2.5 are connected respectively to the secondary outputs elements AND 5.1-5.5, the first inputs of the second elements AND 5.1-5.5 are connected respectively to the outputs of the first elements OR 1.1-1.5 and connected respectively to the inputs of the elements NOT 3.13.5, the outputs of which are connected respectively to the first inputs of the first elements AND 4, l-4 . 5i the outputs of the second elements And 5.1-5.4 are connected respectively with the first inputs of the second elements OR 6.1-6.3, with

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the second input of the first element And 4.5 and are connected respectively with the second inputs of the second elements And 5.2-5.5, the second inputs of the first elements And 4.2-4.4 and connected respectively

 Respectively with the outputs of the second element OR 6.1-6.3, the input bus 8 is connected to the second input of the first element AND 4.1, to the second input of the second element AND 5.1 and to the third inputs of the first elements AND 4.2-4.4, the first inputs of the first elements OR 1.1-1.5 are connected respectively, with the direct inputs of the trigger 2.1-2.5,

15 the second inputs of the first elements IL 1.1-1.5 connected to the outputs of the adders 7.1 to 7.5, corresponding to the control number k (in this case equal to four), the second group

The 20 inputs of adders 7.1-7.4 are connected respectively to the outputs of adders 7.2-7.5, the outputs of adder 7.1, corresponding to the numbers from zero to (kl) -e, are connected respectively 25 but to the second inputs of the second element OR 6.3-6.1 and to the third input of the first element And 4.1, the outputs of the adder 7.1, corresponding to the numbers from the first through (kl) -e, are connected respectively with the first inputs of the elements AND 9.1-9.2 of the first group, element-. Commodity And 10.1-10.3 of the second group of elements And 11.1-11.4 of the third group, respectively, direct output

22 flip-flop 2.1 is connected to the inputs of the And 12.1-12.4 elements, direct output of the flip-flop 2.2 is connected to the inputs of the And 12.1-12.3, 12.5, 11.111, 3 elements, and the direct output of the trigger 2.3 sO is the same with the inputs of the 12.112 .2.12.4-12.5, 11.1-11.2, 11.4, 10.1-10.2, direct output of the trigger 2.4 is connected to the inputs of the elements

And 12.1, 12.3-12.5, 11.1, P.3-11.4, j 10.1, 10.3, 9.1, direct output of the trigger 2.5 is connected to the inputs of the elements 12.2-12.5, 11.2-P.4, 10.210. 3,9.2, and the outputs of the AND 9.19 .2, 10.1-10.3, 11.1-11.4, 12.112 .5 elements and the zero output of the adder 7.1 are the decoder outputs.

The combination of the main counter is not more than k units. Therefore, in order to decrypt the states of the counter, it is necessary to know the number of single bits in the code pattern and their location. This information is contained at the outputs of the first

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discharge and direct outputs of the meter triggers.

The table, as an example, shows the code combinations of the counter for, and the corresponding outputs of the decoder.

Code combinations are split into a group containing equal amounts of units. Since in groups with one. the unit will include combinations: 01000, 10000, a group with two units 01100, 10100, 10100, 11000, etc. The zero state of the counter is removed from the zero output of the first-digit adder.

Decoding of the state of the counter occurs as follows. In the initial state, the counter contains the combination 00000. At the zero output of the adder 7.1, respectively, there is a single signal that goes to the output, and thus determines the zero state of the counter. When the counter is in the state 01000, the single signal from the first output of the adder 7.1 goes to the first input of the element I 9, I, and the single signal from the direct output of the trigger 2.4 goes to the other input of the same element. There is a single signal at the output of AND 9.1, which determines the first state of the counter.

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When the counter is in the state 01100, the single signal from the second output of the adder 7.1 is fed to the first input of the And 10.1 element, the remaining 5 inputs of which receive single signals from the direct outputs of the flip-flops 2.3-2.4. As a result, a single signal appears at the output of AND 10.1, which determines the second state of the counter.

Similarly, the remaining states of the counter will be determined.

5 Ф о р-М ула inventions

The impulse counter according to avtsev, no. 1077054, which differs from the fact that, in order to expand the functionalities of the oval possibilities, k groups of elements I are entered into it, and i is the group of elements And, where i ,,,, k, contains the number of elements And equal to the number of combinations of the number nk-l + i

5 from among n-k + i, the inputs of each element And i-ii of the group are connected to the direct outputs of the flip-flops of the corresponding n-k-1 + i bits from the most senior n-k + i bits; the additional inputs of the AND elements of the L-th group of AND elements, except for the last one, are connected to the output of the first-digit adder corresponding to the number i.

Claims (1)

Claim Impulse counter by ed. St. No. 1077054, O.T. equal to the number of combinations of the number nk-1 + ί from the number n-k + i, the inputs of each element And of the i-th group are connected to the direct outputs of the triggers of the corresponding nk-1 + i bits from the highest n-k + i bits; the additional inputs of the elements And the i-th group of elements And, except the last, are connected to the output of the adder of the first category corresponding to the number i. Code Outputs Code Outputs Code ——— Outputs Code Outputs combination decipher combination decipher combi decipher combi decipher tions rator tion ' rator nation rator nation rator 00000 0 01111 four 101 1) 8 11100 12 01000 one 10,000 5 1 1000 9 11101 13 01 100 2 10100 6. 11010 10 11110 fourteen 01 1 10 3 101 10 7 1101 1 eleven