SU1367041A1 - Read-only memory - Google Patents

Abstract

The invention relates to computer technology and may be used in the construction of digital memory devices. The aim of the invention is to increase the information capacity of the device. The goal is achieved by the fact that the first and second counters, an inverter, are added to the read-only memory containing the first memory block, the address register, the first address driver, the first read amplifier, the number register and the local control block with the corresponding connections. the second and third address formers, memory blocks, read amplifiers, which allows you to store gram commands in the internal language of a higher level than the language on which the dashboard runs, which allows you to increase in ormatsionnuyu device capacitance. 1 il. o (l

Description

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13

The invention relates to computing and can be used in the construction of digital memory devices.

The aim of the invention is to increase the speed and increase its information capacity.

The drawing shows the block diagram of the device.

The permanent memory device contains a register of 1 address, three shaper 2-4 addresses, three blocks 5-7 of memory, three amplifiers 8-10 of reading, two counters 11, 12 addresses, register 13 numbers, inverter 14, block 15 local management The device has three inputs 16-18 and one output 19.

The device works as follows.

In the initial position, until the signal of access to the second input 17 of the device is received, the control signal from the fifth output of the local control unit counters 11, 12 o. When the address from the first input of the device 16 to the register 1 arrives at the first linear section of the program from the first memory block 5 using the driver 2, the amplifier 8 into the first counter 11 reads the address of the linear section of the program in the second memory block 6, and the second counter 12 - the address of the address part of the first operation entering into this linear section of the program. Using shaper 3, amplifier 9 reads the first information word from memory block 6. The second part of this information word is recorded in the operational part of the register 13. If code 1 is recorded in the first part of the information word, one is added to the contents of the counters 11 and 12. At that, the address of the second information word of the linear section of the program in the second memory block 6 and the second information word in the third memory block 7 is formed. The reading of the first information word from the memory block 7 is performed synchronously with the reading of the first information word from the second memory block 6, and the address portion of the next operation of the linear portion of the program is written into the second part of the register 13. Similarly, all subsequent information reads

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five

five

0

five

12

the linear words of the program section from blocks 6 and 7 of memory. When reading the last word of the linear section from the second memory block 6, the code O recorded in its first part is inverted by the inverter 14 and sets the counters 11 and 12 to the zero state. The device returns to its original state and is ready to receive the next address at the input sixteen.

Permanent memory allows storing program commands in an internal language of a higher level than the language in which the machine is running. This reduces the information redundancy of programs.

Claims (1)

Invention Formula A permanent memory device containing the first memory block, the address register, the first address driver, the first read amplifier, the number register, and the local control unit, the information input of the register being the address input of the device, and the output connection the first information input of the address generator, output which is connected to the address input of the first memory block, the output of which is connected to the information input of the first read amplifier, the output of the number register is the information output of the device, The first and second inputs of the local control unit are the input of the access and the synchronization input of the device, respectively, first, second, third and fourth. The outputs of the local control unit are connected to the second control input of the address register entry, the second control inputs of the output of the first address generator, first read amplifier, register number, respectively, characterized in that, in order to improve speed and increase information capacity, it contains the first and second address counters, the second and third address formers, second and third memory blocks, second and third readout amplifiers, an inverter, with the information inputs of the first and second address counters connected to the first and second outputs of the first amplifier read, van, respectively, and their initial setup inputs connected to the inverter output and to the 5th output of the local control unit; the second output of the second read amplifier is connected to the input of the inverter and the counting inputs of the first and second address counters; the output of the first address counter is connected to the information input of the second address shaper whose output is connected to the address input of the second memory unit, whose output is connected to second data input of the sensing amplifier, a first output connected to a first data input of the register, the second output The address counter is connected to the first information input of the third address generator, the output of which is connected to the address input of the third memory block, the output of which is connected to the information input of the third read amplifier, the output of which is connected to the second information input of the number register, the sixth, seventh, eighth and nine The local outputs of the local control unit are connected to the control inputs of the recording of the second and third address drivers and the second and third amplifiers, respectively.