SU1367011A1 - Device for computing logic functions - Google Patents

Abstract

The invention relates to computing and can be used in systems requiring the computation of a large number of complex logical functions of many variables, in particular in systems for technical diagnostics of failures, recognition of special situations on board an aircraft, as well as in process control systems. The aim of the invention is to reduce the equipment with an increase in the number of input variables of the calculated logic function. The device contains switch 1, calculation block 2, register 3, pulse generator 4, counter 5, memory block 6, decoder 7, information input 8, information output 9 In block 6, the commands are stored and the sequential solution of the logical functions of several variables is applied. The main node for calculating logical functions is block 2 of calculations, the amount of equipment of which does not depend on the number of input logic variables, which makes it possible to drastically reduce the required volume of block 6 of memory with an increase in the number of input logic variables. 1 з, п.ф-л, 2 tab. 6 Il. g (L

Description

The invention relates to computing and can be used in devices that require solving a large number of complex logical functions from many variables, in particular in devices for technical diagnostics of functional system failures, as well as for solving problems in control systems.

The aim of the invention / is to reduce the equipment while increasing the input variables of the calculated logic function.

Figure 1 shows the functional scheme of the device; 2 shows an example of a functional diagram of the switch in FIG. 3 an example of a functional diagram of a computing unit; FIG. 4 is a timing diagram for the calculation of the function F Х1ЛХ2ЛХЗ at X,,, where X is the designation of the input variable; FIG. 3 is the timing diagram for calculating the function F with,

five

0

Dn signal A1. Thus, when applying any address code, the input signal will pass through only one D or D chip.

The microcircuit, turned on by discharge A1, transmits to the output on line A an input signal in accordance with the address code A2, A3. A4. Thus, on line A will always pass one of the input signals.

Calculation block 2 contains trigger 10 and the elements of the N-U-26 control node.

The device works as follows.

The basis for calculating the logic functions is the operations performed by the 1K trigger 10.

Logical variables in the order of the queue specified by the function calculation program are fed to the input A of the calculation block 2, which, in accordance with the command given to it

and figure 6 is a temporary diagram of the 25 input from the decoder 7, transmits

ma calculation of the function F at.

The device contains a switch 1, a computing unit 2, a register 3, a pulse generator 4, a counter 5, a memory block 6, a decoder 7, information input 8, information output 9.

An example of the execution of switch 1 for 16 logical variables is shown

Micro-type

on chips 1, D ,. we are D and D, - type 564KP2, 564 LA9 or the like.

At the inputs XI, ... of the X4 of the switch J, a 4-bit code from the output of register 3 is applied.

The 4-bit address code is sent to the inputs A1,; .. A4. The output of the block of memory 6, 12 input logic variables are fed to the inputs X5, ... X16. D and D chips are designed prior to switching analog and digital signals and have three states on output X: logic level logic level 0 signal high output impedance,

In the high output impedance state, output X is closed to allow current to flow in any direction. In order to bring D or B to the third state, it is necessary to send a signal P at the level of the logic unit to the input E of the micro circuit.

The input F of the chip D receives the signal A1, and the input E of the chip

0

five

0

five

these logical variables in direct:. or inverse view of the inputs I and (or) K of the trigger 10, wherein supplying the inverse value of the logical variable to the input K corresponds to the operation of logical multiplying this logical variable by the result of the previous calculation stored in the 1K trigger 10. The supply of the direct value of the logical variable input I corresponds to an OR operation between a given logical variable and the result of the previous operation stored in a 1K trigger 10. Similarly, supplying a logical variable to inputs I and K simultaneously corresponds to an opera uu adding on mod.2.

The operations performed by trigger 2 are described in the table. For convenience, these operations are indicated by mnemonic codes.

The essence of the calculation with the 1K-trigger JO is that. when executing a 10R command with a logical variable that has a single value, the result will also take. single value. By doing.

MD command result will be reset,

if the logical variable is equal. Addition mod 2, in turn, is the supply of logical variables to the counting input.

and inversion of the result by single values of logical variables.

Example. Calculate logical-. which function fg. .LH

The calculation program will look like this:

IOR 08;

The program will be: SLE 00; XOR 08; XOR 05;

XOR

STI

P;

09

When solving more complex functions, register 3 can be used to store intermediate results.

For example, let's solve a function of the following form:

five

eleven

,

. - (x) h. Xg.

in a real case, the solution can be simplified, but to illustrate the method, we will leave it unchanged. For programming, we assume that register 3 has four bits and they are input to switch 1 address 00, 01, 02, and 03, respectively. In the program to the right of the operands are written the following comments:

- zeroing of the controlling trigger;

- resetting the control register;

calculating the first product;

writing to the intermediate result control register;

8SSE

9AND

10AND

11AND

12CME

13IOR

14STI

calculating the second product;

addition of the result; record intermediate result;

calculation of the third product;

0

five

0

five

0

five

0

five

-complication of the result;

- write the solution to the control register.

After calculating the function, register 3 takes either a zero value (if the function variables are zero / or the value is equal to the number of the calculated function. The function code can be used in further calculation algorithms, as well as in external devices.

We illustrate the work of the proposed device with a time chart.

Suppose that the logical variables XI, X2 and HZ are fed to the outputs X5, Hb and X7 of switch 1, respectively. In addition, suppose that the function F XI Л Х2 Л ХЗ has an arbitrarily taken number 5. To calculate this function, it is necessary to run the program presented in table 2.

The result of the calculation of the first, second and third code combinations is shown in Fig.7.8 and 9, respectively.

The calculation of the function F begins at step K defined by the counter 5. In accordance with the address K, the code of the first command 01JO 0000 is read from block 6. On the leading edge of the pulse C 2, this code is stored in the buffer register of block 6 and stored until the next signal arrives C 2. Operation code The IT enters the decoder 7. The latter, in accordance with the software code, provides the unit of the 6th digit of the position code. This unit sets trigger 10 to one.

When executing a command at the Kth step, through switch 1, a logical variable arrives with address 0000 according to the address part of the command.

read from block 6). This logical variable is fed to the input A of the computing unit 2, but does not change its state, since there are no corresponding control signals from the decoder 7.

In the graph (FIGS. 4.5 and 6), the sign -) t- -K-shows the peribds when the value of the logical variable at the output of the switch does not affect the calculation of the function.

In the second step, code 1001, OJOJ is read from block 6. In accordance with this code, the decoder 7 issues a signal to its first output. Logical is variable from the 5th output of switch 1 through the elements JJ, 13,15,16, and 19 is fed to the input K of trigger 10, while the installation of 1K-trigger 10 in O does not occur, since XI 1,

In the third step, a similar command is calculated, but with a logical variable read from the 6th input of the switch,

 In the time diagram (FIG. 4), this logical variable causes the installation of the trigger 10 in O, and in the time diagrams (FIGS. 5 and 6) it is not

installs in O,

In the fourth step, the MP command is executed with a logical variable arriving at the 7th input of the switch 1. This logical variable on the timing diagrams (Figs. 4 and 6) does not cause a change in the state of 1K-Trigger 10, but on the timing diagram (Fig. , 8) causes its installation in O

The command read at the 5th step causes the signal to write the value of the function in the register 3. On the time diagrams (Figs. 4 and 5) this does not occur, since the trigger 10 has the value O,

On the timing diagram (FIG. 6), the code 0101 is written to the register 3, which indicates the single value of the calculated function,

Claims (1)

1. A device for calculating logic functions, comprising a memory block switch, and a decoder, characterized in that, in order to reduce hardware costs by increasing the number of input variables; x logic function to be calculated. 50 five 0 g A pulse generator, a counter, a register and a computing unit are entered into it, the first output of the pulse generator is connected to the summing input of the counter, the output of which is connected to the address input of the memory unit, the second output of the pulse generator is connected if the input of the read sign of the memory unit is from first to Q th output bits of which, where K is the number of bits in the information word format, which determines the code of the current operation, are connected to the information input of the decoder, the output of which is connected to the input of the current opera code and the computing unit, from (K + 1 -) - th to (K + M) -th digit of the output of the memory block, where M is the number of bits in the information word format, defining the HObiep of the current operation, connected to the information input of the register and to the address input of the switch, the bits of the information b-stroke of which are the inputs of the device variables, the third output of the pulse generator is connected to the synchronization inputs of the register and the computing unit, the output of the switch is connected to the information input of the computing unit whose output is connected to the input register entries whose output is the information output of the device. 2, Device pop, 1, characterized in that the computing unit contains a trigger and a control node, the information input of the block is connected to the input of the first variable of the control node, the first output of which is connected to the asynchronous input of the installation on the trigger, etc. my output is connected to the input of the second variable of the control node,: the second output of which is connected to the asynchronous input of the setup in J of the trigger, the inverse output of which is connected to the input of the third variable of the control node, the third output of which is connected to the 1-input of the trigger, whose synchronization input is block synchronization input, input setting the code of the current operation of the block. connected to the input of the fourth variable of the control node, the fourth output of which is connected to the K input of the trigger. Quietly operator Logical multiplication of the result by the direct value of the logical variable Logical multiplication of the result by the inverse of the logical variable Logical addition of the result with the direct value of the logical variable Logical addition of the result with the inverse of the logical variable Addition mod 2 results and a direct value of a logical variable Addition by mod 2 of the result and the inverse of the logical variable Inverse of the result Zeroing result Setting a single result Writing the function number to the register with a single result of its calculation Writing the function number to the register with zero result. Note; By a single result of a logical function calculation or by an intermediate result of a calculation is meant the state of the 1K-flip-flop, in which Q, a. The zero result is understood as the state of the trigger, in which, and Q. The intermediate result is F J. When writing examples of the program for calculating logical functions to the right of the mnemonic, the address part of the operand is written as a decimal constant. . So much b-j Operations In p p p p p p p t Xi xs Mres s sitchike Code from 6 Code new xoffe double shafrap paf Output9 {3-K trigger ten) # t Outlet 1 {od recorded in the calculation of the previous reference X5  -h- 5 Exit code deujugjpamopal h t -k Vykod 3-K trigger U Register code. five Code stock, when calculating the previous one. functions. in K (g2ko9Sh  #