SU1363240A1 - Device for computing the sweeping spectrum - Google Patents

Abstract

The invention relates to a computing technique, is intended to calculate a sliding spectrum of signals, and can be used in real-time spectrum analyzers in the digital processing of seismic and other signals. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the device includes information input 1, memory block 2, multiplexer 3, memory block 4, arithmetic unit 5, memory block 6 coefficients, registers 7, 8, 9, subtractor 10, adder 11, control unit 12, control inputs 13-16. 3 sludge. (L 00 O5 00 th 4 flut.f.

Description

 one

The invention relates to computing, is designed to insert a sliding spectrum of signals and can be used in spectrum analyzers operating in real time in digital processing of seismic and other signals.

The aim of the invention is to improve the speed of the device when calculating the instantaneous spectrum of signals

Fig, 1 shows a structural diagram of the proposed device; Fig. 2 is an example of a specific implementation of the control unit; FIG. 3 is a block diagram of an arithmetic unit (an example of a specific implementation).

A device for calculating the sliding spectrum (FIG. 1) contains information input 1, first memory block 2, multiplexer 3, second memory block 4, arithmetic block 5, coefficient memory block 6, registers 7-9, subtractor 10, adder 11, control unit 12, control inputs 13,14,15,16 devices.

The control unit 12 (FIG. 2) contains the address inputs 17-19, the control outputs 20-24, the generator 25 clock pulses, the counter 26 (clock pulses), the number of bits of which is equal to p + 1, p log2N, counter 27 iteration (number of bits k} log2log NC), 28 detpifrator,} - rounding to a larger integer, - counter 29 codes (number of bits p), counter 30 write address (number of bits p + 1), counter 31 read addresses ( number of bits p + 1) adder 32 (number of bits p + 1), multiplexers 33,34,35, register 36, adder 37, inverters 38, 39.40, element 41, RS-flip-flop 42, lement and 43, an OR gate 44, multiplexer 45,

In addition, the arithmetic unit 5 (FIG. 3) contains multipliers 46–49, adders 50–53, registers 54.55, inverters 56.57, adder 58 across jio-two.

The device calculates the spectral components of cyclic and sliding spectra in the same way as described in the prototype.

In the arithmetic unit 5, compute the basic operation of the FFT algorithm

63240; 2

if there is a single value at the control input 16, the input operands are received from the clock signal (24) passing through the element 58, and results are output by the same clock pulse. Codes 10 and 11 at the control inputs of the adders 52 and 53 correspond to the “add and subtract presses”. With a single value, simple complex multiplication is performed at control input 16 in arithmetic unit 5. Codes 00 or 01 correspond

"With the mode of passing the operand through the adders 52 and 53,

The instantaneous spectrum calculations can be performed as follows .j

2Q Let F (k 0, N-1) be the Fourier coefficients obtained after the i-th implementation of the FFT algorithm over the initial vector cipj (n O, N-1). To calculate the instantaneous spectrum of signals, it is sufficient from each coefficient Fourier F subtract the contribution,

contributed by the oldest count

vector tc (-c (p, add contribution,

: introduced by the following countdown a ,,, and

-n result multiplied by a factor

5U. 9

J

W, where W 1, i.e., calculate new Fourier coefficients F in accordance with the expression F (Y (O ц) in this case

25 to obtain N Fourier coefficients requires all N complex multiplications,

In memory block 2, the initial vector G Of is stored in block 4 of memory 40, the vector of the Fourier coefficients F j. In each first cycle, the reading of the Fourier coefficients F j | from block 4 of memory, on Кс1'zhdom second cycle - recording the results F in block 4 of memory; multiplication is performed at each step (m by the W factor in the arithmetic unit 5, the selection of the corresponding W coefficients is carried out for each:

., house step from block 6 of the coefficients W. 50

Once for the entire iteration is performed

reception in registers 7 and 8, respectively, Of, received at input 1, and c, read from memory block 2, With the aim of simplifying the block diagram of the device of the initial installation circuit, not shown, the control inputs of the adder P and subtractor 10 are also not shown, since during operation the devices do not change their values. Let us assume that the computation mode of the instantaneous spectrum of signals corresponds to a zero value at input 16, to other modes - one; the read mode of blocks 2, 4 - memory - zero, write - a single value, a single value at the control input provides a summation mode, zero - subtraction mode in the adder 37, At the control inputs of multiplexers 35.1, 35.2, 45, a zero value ensures the passage signals from the first inputs to the multiplexer output, i.e. signals used in the calculation of the instantaneous spectrum; with a single value, the multiplexers 45, 35.1, 35.2 pass signals from the second inputs, i.e. signals used in the calculation of cyclic and sliding spectra. Codes 10 and 11 at the control inputs of multiplexer 33 ensure the passage of the write and read addresses when calculating the cyclic and sliding spectra of signals; codes 00 and 01 connect the write and read addresses when calculating the instantaneous spectrum of signals; the signal 16, arriving at the senior address input of the block of 6 W coefficients, provides the selection of the W coefficients, which are recorded in the block of 6 W coefficients, in the sequence necessary to calculate the values of the instantaneous spectrum in accordance with the given expression; codes 10, 11 at the control inputs of multiplexer 3 ensure the passage of information from the outputs of memory blocks 3.4, respectively, code 00 or 01 from the output of adder 11.

Consider the operation of the device when calculating the instantaneous spectrum of signals. In their one position, the counter 26 clock pulses, the counter 27 iterations, the counter 31 of the read address, the register 36 is in the zero state, the trigger 42 is in one, the counter 30 of the write address is in the state 01 ... 11. The zero value on the control input of the multiplexer 33 ensures the passage of values from the output of the counter 31 of the read address, i.e. At the input of block 2 of memory, there is a code 00 ... 00; at the input of the control of writing, reading of block 2 of memory — code O, which provides

3632404

read mode. Of

memory block 2

ten

15

20

25

thirty

35

40

45

50

55

at address 0 ... 00 is read a j. The zero value at the control input of the multiplexer 45 ensures the passage of signals from the output, register 36 to the address input of memory block 4; A zero value is present at the write control input, reading the memory block 4, and the Fourier coefficient F is read. At the address inputs of block 6 Fourier coefficients there is a code 0, .. 00, by which the coefficient W is read. Let the operand a be present at the device input, the code 00 ... O entered at the input 13 of the device parameter setting input to the counter 29 with a clock signal 15 . At the input of register 36, a code 11 ... 10 is formed with the help of adder 37.

We will consider the initial state as the first step and the first step of the device operation.

In the first step in the second clock cycle, the 26 clock clock counter is in the state 0 ... 01. Let the input signal 14 receive the sync signal accompanying the input operand o (, and pass through the element 43 (at the second input of which there is a single value), changes the state of the code counter 29 to 111 ..., and the write address counter 30 to 10 ... 00. The same signal is executed "and of |, respectively, in registers 8 and 7. The overflow signal from the output of code counter 29 sets the trigger 42 to the zero state, thereby prohibiting reception of input data until the end of the iteration; in register 9 FJ is received by the clock signal 23. In the same clock cycle at the output of the adder 11, We get a task in which, having passed through multiplexer 3 (at the control input code 00), is fed to the input of the arithmetic unit 5. The value of the coefficient V ° is also present at the input of the arithmetic unit 5, status, address outputs 17 of the counter 31 of the read address does not change At the input of the read address counter 31, a code 0 ... 01 is present. In register 36, a code 11 ... 10 is received which, having passed through multiplexer 45, is fed to the address input of memory block 4. At the input of the write control, read 23 - code I. At address 11 ... 10, the Fourier coefficient F of the previous i-th implementation can be written. At the input of the register 36 with the help of the adder 37 is formed code O01 .., 01,

In the second step, in the first cycle, the state of the counter is 26 cycles - 0 ... 10, the states of the counters are 30,31,29,27, the trigger 42 does not change,

In the arithmetic unit 5, the synchronization signal (24) is receiving

(V o - o

and performed

,.,, s,) and W- ° complex multiplication operation.

In memory block 2, the operand is recorded if at address 10 ... 00, formulated in counter 30, which passes through multiplexer 33 with code 01 on control codes In register 36, code 00 ... 0 is received, which passed through multiplexer 45, is fed to the address input of memory 4, input 23 controls the write, reads code 0. From memory 4, reads the Fourier coefficient F ii / j, which is fed to the input of register 9 from block 6 of the coefficients W ad36

f-wf2 code is generated

su 00, .. reads W, for input

m / y treason de register .., 11.

In the second step, in the second clock cycle, the clock clock counter 26 is in the state 00 ... And, the states of the counters 27-31, trigger 42 are not changed. Similarly to the second cycle of the first step, register F is recorded in the F states of registers 7 and 8. At the output of the adder 11, we obtain the value (Hii 0 (5+.,) Which is fed to the input of the arithmetic unit 5, the value of the coefficient W is also present at the input of the arithmetic unit 5.

In register 36, the code 11 .. ... 11 is received, according to which the writing in the memory 4 block of the Fourier coefficient 1 is performed

N-1

previous

i-and implementation. At the input of register 36, a code 00 ... 10 is formed.

In the third step, in the first clock cycle, the counter 26 is in the state O ,,. ...100.

In the arithmetic unit 5, the sync signal 24 is used to receive iF.j- with (4-. The same sync pulse produces the multiplication result ((+ n () W which is fed to the input of the memory block 4, B) memory can repeat

The write operand record at 10 ... 00. The register 36 receives the code O0 .., tl0, which is the Fourier coefficient readout address F V / 4 N / 4 arrives at the input of register 9. From the block of 6 coefficients W at address 0 ... 10 is read. At the input of register 36, a code 000 ... O is formed.

In the third step in the second cycle, the operation of the device is similar to the second cycle of the first and second steps.

In this cycle at 0 ... 00 in

five

memory block 4 is executed in register 9 - F

)

0

five

0

five

0

a record

l t ft- JA KjM to the input of the arithmetic unit 5 receives PW / ° w. The coefficient value is also present at the input of the arithmetic unit 5. In register 36, the code 000 ... O is received, and at the input of register 36 a code is generated .00 .. . eleven.

In the remaining cycles the operation of the device is similar. In N steps, in block 4 of memory, the instantaneous spectrum of the source data vector will be recorded, (n 1, N).

After performing the second cycle N-ro step, the overflow signal from the output of the counter of 26 cycles, passing through multiplexer 35.2, sets the counter 29 to the initial state - 00 ... 00, the trigger 42 - 1, the counter 31 records the code 00 .., ... 01 and the operation of the device is repeated. From memory block 2 at address. 00 ... 01, operand a is read., Input operand is written at address Yu ... 01 in memory block 2, the address is formed in the write address counter 30. In block 4, the memory is semi-. This is the instant spectrum from the vector of initial data C «f, (2, N + 1).

Claims (1)

Invention Formula A device for calculating the sliding spectrum, comprising a control unit, a coefficient storage unit, a multiplexer, the first and second memory blocks, the output of the first memory block connected to the first information input of the multiplexer, the first and second outputs of which are connected to the first and second operand inputs an arithmetic unit whose output is connected to the information input of the second block the memory, the first and second outputs of the coefficient memory are connected to the first and second inputs of the coefficients of the arithmetic unit; the first and second address outputs of the control unit are connected to the address inputs of the first and second memory blocks, respectively; the first and second control outputs of the control unit are connected to the write control input - the readout of the first memory block and the first control input of the multiplexer, and the first, second and third inputs of the control unit are respectively the job input pa The meter has the first and second synchronization inputs of the device, characterized in that, in order to improve speed, an adder, a count, three registers are entered into it, the information input of the first register being the information input of the device, and the output of the first register connected to the information input the first memory block and the first input of the subtractor, the output of which is connected to the first input of the adder, the output of which is connected to the third information input of the multiplexer, the output of the first memory block is connected to the information The input of the second register, the output of which is connected to the second input of the subtractor, the output of the second memory block is connected to the information input of the third register, the output of which is connected to the second input of the adder, the fourth input of the control unit is connected to the control input of the arithmetic unit, the second control input of the multiplexer , the input of the higher bit of the memory address of the coefficient and is the input of the device mode setting, the third control output of the control unit is connected to the clock inputs of the first and second registers., the fourth control-output of the control unit is connected to the third-register clock input and the write-read control input of the second memory block, the fifth control and the third address outputs of the control unit are connected to the syncro input of the arithmetic unit and the address input, respectively coefficient memory block, while the arithmetic unit contains four multipliers, four 0 five 0 five 0 adder, two registers, two elements NOT and an adder according to two. the first input of the first adder is connected to the first inputs of the first and second multipliers and is the first input of the operands of the arithmetic unit, the second input of the operands of which are interconnected first input of the second adder and first inputs of the third and fourth multipliers, the second inputs of the first and fourth multipliers are connected interconnected and are the first input of the coefficient of the arithmetic unit, the second input of the coefficient of which is interconnected second inputs of the second and third multiplied The first and third multipliers are connected to the first and second inputs of the third adder, the output of which is connected to the second input of the first adder, and the outputs of the second and fourth multipliers are connected respectively to the first and second inputs of the fourth adder, the output of which is connected to the second input of the second the adders, the outputs of the first and second adders are connected to the information inputs of the first and second registers, respectively, the outputs of which are combined and. are the output of the arithmetic unit, the synchronization of which is the first input of the modulo two adder, the output of which is connected to the clock inputs of the first, second, third and fourth multipliers, the first and second registers and the input of the first element, the receive synchronization inputs of the first, the second and third adders are connected to the input of the second element NOT, the second input of the modulo-two adder is the control input of the arithmetic unit, the output of the first element is NOT connected to the output synchronization inputs p The first and second adders, and the output of the second element NOT to the synchronization input of the reception of the fourth adder, while the control unit contains five multiplexers, a counter, a write address counter, a read address counter, a code counter, three HE elements, an RS trigger, an iteration counter , two adders, two elements AND, decoder, element OR, register and clock generator, output KOTpjjpro 0 five 0 five connected to the first input of the first element I, the counting input of the counter and the clock input of the register, the output of which is connected to the first input of the first adder, the upper bits of the second input of which are connected to the input inputs of the logical zero of the device, and the output of the first adder are connected to the information input of the register, output the overflow counter is connected to the first information input of the first multiplexer and the counting input of the iteration counter, the overflow output of which is connected to the second information input of the first mule A multiplexer whose output is connected to the setup input of the read address counter, S input of the RS flip-flop and the first input of the OR element, the output of which is connected to the setup input of a code counter whose overflow output is connected to the R input of the RS flip-flop, the output of which is connected to the first input of the second element And, the output of which is connected to the counting inputs from the ethernet code, the write address counter and is the third control output of the control unit, the output i-ro (i O, p-1; p log, N, N is the size of the conversion) the counter of the record counter is connected to the inputs ix of the bits of the first and second information inputs of the second multiplexer and the input of the i-ro bit of the first sump, the output j-ro (j o, p) the bit of which is connected to the input of the i-ro bit of the read address counter, the output of the ta-th (t 1, p) bit of which is connected to the inputs of the bits of the third and fourth information inputs of the second multiplexer, the first control input of which is connected to the output of the second digit of the counter, the output of the first digit of which is connected to the input For the first element NOT, the first bit inputs of the first input of the second adder, and the information input edges of the first multiplexer, the output of which is the fourth control output of the control unit, the output of the first element is NOT connected to the first information input of the fourth multiplexer and is the fifth control - ten 363240 10 the control output of the fourth multiplexer is connected to the input of the decoder and connected to the information output of the iteration counter; the output of the p-th bit of the write address counter is connected to the input of the second element NOT whose output is connected to the input of the p-th digit of the first input the first adder, the transfer output of which is connected to the input of the first bit of the second input of the second adder and is the input of setting the logical unit g block, the output of the decoder is connected to the second input of the first element I, the output of which is connected to the counting input of the read address counter, the output of the first bit of which is connected J. It is connected to the input of the third element NOT, the output of which is connected to the input of the first bit of the second information input of the second multiplexer, the information input of the code counter is 25 with the first input of the control unit, the second and third inputs of which are respectively the second inputs of the first AND element and the OR element, the output i-ro (i thirty 35 40 45 50 55  2, p + 1) the counter is connected to the i-ro input of the second information input of the fourth multiplexer, the output of the co-. This is connected to the first information input of the fifth multiplexer, the second information input of which is connected to the register output, the output of the second multiplexer is the first address output of the control unit, the second address output of which is the output of the fifth multiplexer, and the information output of the counter is the third address the output of the block whose first control is to the output of which is the output of the second discharge of the counter, the output of the second discharge of the counter is connected to the second information input of the third multiplex Ksor whose output is a second control output of control unit, fourth input of which are connected by a third input of the first AND gate, control inputs of the first, third and fifth multiplexers and a second control input of the second multiplexer. Compiled by A. Baranov Editor A. Makovska, Tehred M. DDIkKorrektor A.    , 4m, fi, fmf, fft in tg, fmerf f fimmm if f, Order 6364/42 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4