SU1315999A1 - Device for calculating values of fourier coefficients - Google Patents

Abstract

The invention relates to computing and can be used in real-time digital signal processing systems. The purpose of the invention is to improve accuracy. This goal is achieved due to the fact that the device consists of a two-port memory block 1, a body shift 2, an arithmetic unit 3, a memory block 4, converters of a reverse code in forward 5, 6, a memory block 7, an OR-8 element, a register 9, an address driver 10, a synchronization unit 11, a scale calculation unit 12, an information input 13, a start input 14, and an output of the scale factor 15. 9 Il. (Ls tna js with

Description

ten

11315999

The invention relates to computing and can be used in real-time digital signal processing systems.

The aim of the invention is to improve the accuracy of calculations;

Figure 1 presents the scheme of the proposed device; Fig. 2 is a scale calculation block diagram; FIG. 3 is a graphical diagram of the FFT algorithm; FIG. 4 is a diagram of an address maker; Fig. 5 is a diagram of the synchronization unit J in Fig. 6-10 are timing diagrams explaining the operation of the device.

The device contains a dual-port memory unit 1, a shifter 2, an arithmetic unit 3, a permanent memory unit 4 (tabular coefficients), converters 5 and 6 of the reverse code into a forward one, a permanent memory unit 7, an OR 8 element, a register 9, shaper 10 addresses, synchronization unit 11, scale calculation unit 12, information input - output 13, start input 14 and output 15 of the scale factor ..

W. - complex weight coefficient f5

tsent (fig.Z)

The synchronization unit (FIG. 5) contains a clock pulse generator 52, a pulse distributor 53, an OR element 54, an AND element 55, a waiting multivibrator 56, an And element 57, a shift register 58, outputs 59, a trigger 60, an element 61, and an element 62 , trigger 63, element And 64, counter 65, elements And 66 and 67, vhbd 14, codes 68-72,

Consider the operation of the device on the example of calculating the Fourier coefficients for an array of length N 16 points. The device operates in start-stop mode. For each trigger pulse, a one-time calculation of the Fourier coefficients is performed and the device stops before the next trigger pulse arrives.

With the arrival of a pulse at the device input 14, the block 11 generates a source signal at the output 68, which initializes all the blocks of the device. Then, at output 59, synchro pulses SI1 to SI16 begin to be generated, which are fed to the units of the device, providing Block 1 consists of a complex integrated 30 consistent time mode 20

25

the numbers in which the cells are stored. real and imaginary components of complex numbers. The memory capacity is 2N words (N is the length of the array being processed).

The scale calculation block (Fig. 2) contains a multiplexer 16, an adder 17, registers 18 and 19, an element chip of 20-23, reversible counters 24 and 25, elements of AND 26-29, elements of OR 30 and 31, fixed memory node 32 TI, register 33, inputs 34-38, outputs 39 and 40, and register 41,

Shaper 10 addresses (Fig, 4)

you are the whole device.

Fig. 3 shows the graphical scheme of the used FFT algorithm. When performing the basic operation of the 35 Algorithm of the FFT with base two, it is necessary to count. Two operands, one coefficient and write two operands - the result of the basic operation.

Fig. 6 shows the time frame of the basic operation. The base operation is performed in 16 clocks. First, the first and second operands are read (CI1 to CI5), Addresses for data operations of the form

contains reversible counters 42 and quenchings come from the driver (with input logic), block 44 element addresses (output 50), Then on these OR signals, element 45, trigger 46, operands, basic one-multiplexer is executed, 47, inputs 48 and 49 and radio. The coefficients are read from outputs 50 and 51. of block 4 at the address given to the block. The arithmetic unit performs 10 addresses by the supporter (output 51),

After performing the basic operation by block 3, the results of the operation are recorded at the same addresses in block 1. Simultaneously with the recording of operands in 55 RAM, the magnitude of the modulus of the complex numbers is estimated. The arithmetic unit works with numbers represented by fixed-point codes.

,-and

 BUT;

4B .;

B ,, A, - B; ,

where a- and b; - complex operands, with the operand B first being calculated; 4. , and then A,,

W. - integrated weight coeffixes of the entire device.

Fig. 3 shows the graphical scheme of the used FFT algorithm. When performing the basic operation of the 35 Algorithm of the FFT with base two, it is necessary to count. Two operands, one coefficient and write two operands - the result of the basic operation.

Fig. 6 shows the time frame of the basic operation. The base operation is performed in 16 clocks. First, the first and second operands are read (CI1 to CI5);

To eliminate overflow, a conditional scaling algorithm is used, at which at each iteration the magnitude of the modulus of the complex operands at the output of the arithmetic unit is estimated. Moreover, in order to increase the accuracy of the computations, all the operands are worked into two groups in accordance with the graphical scheme of the FFT algorithm (Fig. 3). The first group includes operands located in the RAM block at addresses 0000 to 0111, i.e. meaningful in high order address. The second group includes operands located in the RAM block at addresses 1000 to 1111, i.e. having 1 as head de. Each group has its own scale factor. If at least one operand of the group had a module greater than or equal to 0.5, then at the next iteration all the input operands of this group are shifted by one bit to the right. If all operands of the group had modules less than O, .25, then all input operands of this group are shifted one bit to the left. If all operands of the group had modules less than 0.5, but there is at least one group operand whose modulus is greater than or equal to 0.25, then the input operands of this group arrive at the input of the arithmetic unit without a shift. When these conditions are met, the arithmetic unit is operated without overflow.

The modulus of a complex number is determined by the expression

| A, I - (Re A;): + () 2,

where A, - is a complex number;

RpA I is the real part of the number;

 j is the imaginary part of the number.

From the analysis of this expression it can be seen that when the value of iRgA;) / 0.5 is the modulus of the complex number 0.5, regardless of the value; The value of 1 is 17 / 0.5 modulus of the complex number 7, 0.5, regardless of the value of RgA.

For other values of RgA, the inequality (A., 5 depends on both the real and imaginary parts of the complex number. To save equipment, the magnitude of the modulus of the complex number is estimated approximately

by analyzing the higher bits of the real and imaginary parts of a number.

For definiteness, consider the operation of the device at K 5.

In the initial state, all the registers are set to O. To the control input of the shifter 2, a code is supplied that corresponds to the shift of all operands in the first iteration by one bit to the right. The operands involved in the calculations in the appropriate sequence required by the FFT algorithm are fed to the input of the shifter 2, shifted by one bit to the right. and arrive at the first input of the arithmetic unit 3. At the output of block 3, the values of the module of the operands calculated at the current iteration are estimated.

First, using converters 5 and 6, they are converted into direct code. (This reduces the capacity of the ROM unit). For this on

The control inputs of converters 5 and 6 are connected to sign bits of the real and imaginary parts, respectively, having a weight of 0.5, which are brought directly to the inputs of element 8. The remaining four bits of the converters 5 and 6 codes are set to address blocks of block 7. By addresses that correspond to the mantis codes of the real and imaginary parts of the number, in which the module is greater than or equal to 0.5, code 1 is written, and code 0 is written for the remaining addresses.

In the second bit of block 7, at the corresponding addresses, at which the modulus of the complex number is less than 0.25, O, and for the rest, adII l II

recorded code, resam recorded code

 R

From the output of block 7, the second bit is applied to the information input of register 9. The value of the modulus value is entered in register 9. After processing the operands belonging to the first group, the contents of register 9 are written to register 33 of the scale calculator. After processing the operands belonging to the second group, the contents of register 33 are rewritten to register 41, and the contents of register 9 to register 33. Computation block. the scale of the contents of the registers 33 and 41 generates the control signals of the shifter 2 alternately for the operands of the first and second groups.

In addition, based on the codes in register 33, the scaling factor is calculated for the first group at counter 24 and for the second group at counter 25. At the last iteration, when processing operands belonging to different groups, the scales are aligned before performing the calculations. To do this, in the scale calculation unit, shift codes 2 for each group are generated at the last iteration; providing the shift of the operands when reading from block 1 by the corresponding number of bits. At the same time, at output 15, a code value is set corresponding to the scale of the calculated spectrum.

The synchronization unit 11 (FIG. 5) of the ra- tion in the iteration register 58

bots in start-stop mode. The timing diagram of the unit is shown in FIG. 7. Assume, that at the moment the device has completed the calculation and is in the waiting state. The first input element And 55 receives a signal 1, generated by the iterative shift register 58 (n + 1 bit) at the end of the calculations. The same signal arrives at the input of element 54 and blocks the operation of the distributor 53. With the arrival of a trigger pulse at input 14, the output of element 55 produces a signal that triggers the standby multivibrator 56. , as well as to other units of the device (exit 70).

At the end of the signal, the Source starts up the distributor of 53 pulses, producing 16 clock pulses that are offset in time, which arrive at the blocks, ensuring a consistent operation mode of the device. On account 65, the number of basic operations performed is calculated. When the counter contains the discharge bit.

As the basic operations are performed, the state of the counter 65 becomes 0000, 0001, 0010, 0011, 10000, and so on. (FIGS. 8 and 10) When counter 65 is equal to 0100, a signal is generated at the output of element 62, according to which Trigger 63 is set to state 1 (PPI CP2), and high potential is output at output 70, which corresponds to - to the processing of operands of the first group and is used in the scale calculating unit (signal A01). When the counter 65 is equal to 1000, a signal is generated at the output of the element 61, the trigger is set to state 1 (PPI CP2), and a high level is set at the output (signal P02). By this signal, the UIS cycle is used to shift the contents of the iteration register 58 and at its output 72 a code 01000 is set corresponding to the execution of the second iteration (FIG. 9). Through elements 66 and 67, the counter 65 with the UIS clock is reset to O. Next, the process repeats.

After the last execution, the code 00001 is set. The high level from the fifth bit goes to the element OR 54 and prohibits the generation of sync pulses. The device goes into standby mode.

The address generator (FIG. 4) provides the formation of the addresses of the operands and coee4) of the candidates in the sequence necessary to perform the FFT algorithm with base two in accordance with the graph used (FIG. 3). The signal Source Counters 43 and 42 and trigger 46 are set to O. Input 48 receives a four-digit code from an iterative shift register 58, which controls the counting order of counters 42 and 43. Counting pulses arrive

to the input 49 from the output of the element 64. On the element 64 blocking the arrival of clock pulses for the duration of the action of the signal P02. At the output 50, the addresses of the operands are formed.

The first read address is formed on the counter 42 and through the first input of the multiplexer 47 arrives at the output 50. The second read address is formed on the bits 44 and

enters the output 50 through the second, the input of the multiplexer. The multiplexer is controlled by a trigger 46, which is switched on the counting input from the output of the element 45 by clock pulses.

PPE and SI15 (Fig.6). When writing, recording is performed in block 1, first of the second operand, and then of the first. Addresses for reading weight coefficients are generated on a counter 43, and, due to the input logic, the counting pulses go to that counter's counter, which comes 1 from the iterative shift register.

Scaling unit operation

By the Initial signal, all registers are set to O, the code corresponding to the value - 1 is entered into the counters 24 and 25 (with the code 011). This code corresponds to the scale of the result, if at the first iteration the input array is shifted by one bit in the direction of the first and second bits, and in the remaining iterations, the operands will be transmitted to the arithmetic unit without shifts.

In the first iteration, the operands are always shifted by one bit towards the lower bits. This is ensured by the fact that for a single value of the first bit of the iteration register 58, the output of node 32 is set to code 10001, regardless of the value of the other inputs of node 32. The code from the output of node 32 goes to the control input of the shifter 2, which performs the shift operands. During the first iteration, an estimate is made of the magnitude of the modulus of the complex numbers — the results of performing the base operations. The evaluation results are recorded in register 9 at instants SI14 and SI16, corresponding to the presence of the first and second operands at the output of the arithmetic unit.

When a signal appears P01, corresponding to the completion of processing the operands of the first group, a high level through the element 30 post falls to the input of the element 27, the output of which generates a signal that records the contents of the register 9 into the register 33 and clears the register 9 (output 39). If there is a code 11 in the 33 register (the modulus of the number is greater than or equal to 0.5), a signal is generated at the output of the element 21, according to which one is subtracted from the counter 24. If the code 33 in the register 33 (the modulus of the number is less than 0.25), the output of the element 20 generates a signal that adds one to the contents of the counter 2. If there is a code 01 in register 33 (the modulus of a number is greater than or equal to 0.25, but less than 0.5) the contents of the counter remain

without changing, thus, on the slit 24, a code is fixed which indicates how many bits it is necessary to shift the operands (in the direction of the least significant bits) so that the result scale becomes equal to one. Further calculations are performed with operands belonging to the second group.

Upon completion of these calculations, block 11 generates a signal P02, which is used to overwrite the contents of registers 33 into 41, and register 9 - into register 33. According to the contents of register 33 on elements 22 and 23, format the control signals for counter 25 (similar to signals for counter 24). For the duration of the signal, P02 is blocked by the construction of the building signals for register 9 (element 29). At the end of the P02 signal, the second iteration of the FFT algorithm begins, On the node code

32, one of the codes defined by the module evaluation code for the first group is set. This code is fed to the control input of the shifter 2.

Upon completion of processing the operands of the first group by block 11, a signal P01 is generated. This signal uses elements 30 and 27 to rewrite the contents, registers 9 to 33, and

33- 41, At the output of the node 32, a code will be established by which the shifter

2 will perform shifts for the operands of the second group. Further, at subsequent iterations, the nature of the work. the block does not change.

At the penultimate iteration (- - 1), the signal P02 (elements 28 and 26) generates a signal that sends the difference code of the first and second groups to the register 19 from the output of the adder 17 (the difference between the codes of the counter 24 and 25). At the same time, the same signal in register 18 through multiplexer 16 records the code of that counter (scale of that group), the code of which has a smaller value. The multiplexer is controlled by a significant digit of the adder 17. With a single value of the significant digit of the adder, the register 18 records the state of the counter 24; when the value is zero, the state of the counter 25. This code will correspond to the scale of the calculated spectrum and through the output 15 is transmitted to the next processing device.

.913

The scale difference code from register output 19 goes to the address inputs (5-8 bits) of node 32. At the last iteration, when the address is fed to the second bit, the unit of the fourth and fifth bits of the address does not affect the output code of the node 32 Consider the possible options. Let, the scales of the first and second groups are equal .. In this case, the register 19 fixes the code 1111. When reading the operands of the first group. at the output of node 32, the code 10001 is set corresponding to the shift of the operands by one bit in the direction of the lower bits (to prevent the grid from overflowing at the last iteration). When reading the operands of the second group, at the output of node 32, the code 10001 will be set, according to which on the shifter 2 the operands will be shifted one bit in the direction of the lower bits.

Thus, the operands of the two groups will be shifted by one bit towards the lower bits before being calculated. Register 18 will be rewritten counter code 24 of the first group, which will be taken for the scale of the whole spectrum. Let the scale code of the first group be greater than the scale code of the second group. Then the difference code formed at the output of the adder 17 will be positive (the highest corresponds to O). When reading the operands of the first group and leaving the node 32, one of the codes will be set, determined by the value of the code for the difference between the scales of the groups. When: reading the operands of the second group at the output of node 32, the code 10001 is set, corresponding to the shift of the operands on the shifter by one bit towards the lower bits. Counter 18 will be rewritten counter code 25, which will be taken out of the scale of the whole spectrum.

Let the scale code of the first group be less than the scale code of the second group. Then the difference code generated at the output of the adder 17 will be negative (the most significant bit corresponds to the value 1). In this case, when reading the operands of the first group, at the output of the node 32, the code 10001 is set, which corresponds to the shift of the operands on the shifter by one bit in the direction of the lower bits.

599910

When reading the operands of the second group, the output of node 32 will be set to one of the codes determined by the value of the difference code of the 5 groups. Counter 18 will be rewritten counter code 24, which will be taken for the scale of the entire spectrum.

Claims (1)

Invention Formula A device for calculating Fourier coefficients comprising a dual-port memory block, a shifter, an arithmetic unit, first and second blocks a fixed memory, an address driver, an element OR, a register, a synchronization unit and the first and second converters of the reverse code to the forward one, the informational outputs of which are connected respectively to the first and second address inputs of the first block of the permanent memory whose output is connected to the lower ones I will give the information entry of the register, senior the bit of the information input of which is connected to the output of the element OR, the first input of which is connected to the output of the higher bit of the first block of the permanent memory, the outputs of the real and imaginary parts of the number of the arithmetic unit are connected to the first inputs of the first and second converters of the return code, respectively, the outputs of the sign bits of which are connected respectively to the second and third inputs of the OR element, the outputs of the higher bits of the real and imaginary part of the number of the arithmetic block are connected to the second inputs of the first and second converters of the inverse code to the forward one, respectively, the first output of the address driver is connected to the address input of the second permanent memory unit, the output of which is connected to the input of the coefficient of the arithmetic unit, the outputs and imaginary parts of the number of which are combined and connected to the information input of the first port a two-port memory block and an information input of the shifter, the output of which is connected to the information input of the arithmetic unit, the information input of the second port of the two-port memory block is the information input of the device, the startup input of which is the trigger input of the synchronization block, the outputs of the first to fifth plug 1113 respectively, to the inputs from the first to the fifth address driver, where the address driver contains the first and second reversible counters, an OR block, a multiplexer, a trigger, and an element whose output is connected to the trigger input of the trigger, the output of which is connected to the multiplexer control input, the first information input of which is connected to the output of the OR block, the first input of which is connected to the second information input of the multiplexer and connected to the information output of the first reversing counter, The addition input is connected to the summing input of the second, reversible counter, the second input of the block of OR elements and is the first input of the address generator, the second input of which are interconnected subtractive inputs of the first and second reversible counters, the installation inputs of which are connected to the installation input of the trigger and are the third input of the address generator, the fourth and fifth inputs of which are the first and second inputs of the AND element, respectively, and the multiplexer output and information output The second reversible counter stroke is correspondingly the first and second outputs of the address generator, characterized in that, in order to improve the accuracy, a scale calculation unit is inserted in it, the first output of which is the output of the device scale factor, the second output of the calculation scale unit is connected to the input of the shift code of the shifter, the third and fourth outputs of the scale calculation unit are connected respectively to the clock input and the register write enable input, the output of which is connected to the first input of the block in the number of the scale, the second input of which is connected to the second output of the synchronization unit, the address input of the two-port memory block is connected to the second output of the address generator, the first output of which is connected to the third input of the scale calculator, the inputs from the fourth to the tenth are connected to the outputs of the sixth on the twelfth block - synchronization, the third output of which is connected to eleven 599912 At the input of the scale calculator, the scale calculator contains eight AND elements, two reversible counters, two HW elements, with an adder, a multiplexer, four registers and a fixed memory node, the first address input of which is connected to the output of the first register, ns input which is connected to the output 10 second register information the input of which is the first input of the scale calculator, the output of the first bit of the second register is connected to the first inputs of the first and second 15 elements And, the outputs of which are connected to the summing inputs of the first and second reversible counters, respectively, the installation inputs of which are connected and are the input of the reference 0 constants of the scale calculation unit, the output of the second bit of the second register is connected to the first inputs of the third and fourth elements AND whose outputs are connected to the subtractive inputs of the first and second reversible counters, the information output of the first, reversible counter is connected to the first information input of the multiplexer and the first input of the remote control of the adder, the output of which is connected to the information input of the third register, the output of which is connected to the second address input of the fixed memory node, the third address provided a clear 5 whose input is combined with the first input of the fifth element AND, and is the second input of the scale calculating unit, the information output of the second reversible counter is connected to 0 to the second input of the adder and the second information input of the multiplexer, the output of which is connected to the information input of the fourth register, the output of which is the first output of the scale calculator, the second output of which is the output of the fixed memory node, the fourth address input of which is the third input the block for calculating the scale, the fourth input of which is the combined second inputs of the second, fourth and fifth AND elements, the first inputs of the sixth AND element and the first OR element, the second input 5 of which is connected to the second inputs of the first and third elements I and B-, the fifth input of the scale calculating unit, the third output of which is 13-13 This is the output of the sixth AND element, the second input of which is connected to the output of the second OR element, the output of the first OR element is connected to the first input of the seventh AND element, the output of which is connected to the clock inputs of the first and second registers and is the fourth output of the scale calculator the input of which is the second input of the seventh element And, the output of the fifth element And connected to the first input of the eighth element And, the output of which is connected to the clock inputs of the third 91A and the fourth register, the output of the character bit of the adder is connected to the control input of the multiplexer, the third inputs of the first, second, third and fourth elements of And are connected and are the seventh input of the scale calculator, the eighth input of which is the second input of the eighth element and second the inputs of the second OR element are respectively the ninth and tenth inputs of the block, the eleventh input of which is the combined zeroing inputs of the first and second reversible counters. Vu .. 48  42 I ycCT.w / l 3 5f 9ut. g 4-6 in to p te t V I And I I I I I I M And I I I I I I I : st no g no g Pia.9