SU1361636A1 - Memory device - Google Patents

Description

The invention relates to computing, in particular, to memory devices, and can be used in the construction of computing systems.

The purpose of the invention is to increase the reliability of the device.

Fig. 1 shows the functional diagram of the storage device in Fig. 2 and 3 shows functional diagrams of the control unit and the accumulator in Fig. 4, respectively, is a schematic diagram of the memory cell of the accumulator.

The device contains a control unit 1, an input data register 2, an address register 3, 4 write amplifiers, 5 address signal amplifiers, read amplifiers 6, an output data register 7, an address decoder 8, first 9 and second 10 odd-od control units, drive 11, register 12 control information, buffer register 13 data, the first 14 and 13616362

38. By recording the register in register 38, the first bit is set, the unit level from the output of which, after the delay of elements 44, connects element 40 to operation. The leading edge of this signal is the control signal on inputs 19 and 21.

10 A strobe signal passing through a circuit consisting of delay elements 42 and 43, element 40, delay elements 45-47, and flip-flop 39 organizes the generation of a series of control signals.

15 signals that provide execution of the write command in the device. The signal at output 19 is stored in register 2 recording information. The signal at output 20 is memorized.

20 in the register 3 address. The signals from the outputs of the elements 44 and 43 of the delays on the outputs 21 and 22 gates the operation of the selected amplifiers 4 and 5.

NIN, as well as input 17 of write-read commands, input 18 for device gating, outputs 19-22 from the first to fourth control unit 1, information outputs 23, one of the control outputs 24, information inputs 25, other control outputs 26 of the device, information inputs 27 of the accumulator 11, address inputs 28 of the device, address inputs 29 and outputs 30 of the accumulator 11, output 31 of the device error signal, outputs 32-36 from the fifth to the ninth block 1 of the control. The control unit 1 contains (FIG. 2) a decoder 37, a register 38, a trigger 39, elements AND 40 and 41 from the first to eighth delay elements 42-49. The drive 41 contains (FIG. 3) memory cells 50-65, each of which contains (FIG. 4) MOS transistors 66-68 ..

The device works as follows

In the recording mode on input 25, the device receives information for recording, on input 28 - the address, on input

17 - command and input 18 - gating signal. The information obtained is analyzed by block 10 for the presence of odd oddities in it. The result of the analysis, block 10, outputs 26, and simultaneously in block 1, the decoder 37 decrypts the received command, which is stored in input from the signal received at input 18

from the words accumulator 11, for example a word consisting of memory cells 58-61

(fig.Z)., By this signal, the incoming

0 to the inputs 30 (figure 4), in each

The transistors 66 and 68 are opened in the memory cell of this word. Transistor 66 provides input 27 from the outputs of the information amplifiers 4 for recording to inputs 27. The transistor 68 provides through the transistor 67 at the output 30 the flow of information stored on the parasitic capacitors. As a result, old information is present at outputs 30 for some time, and after recording new information. The signal from the output of the delay element 45 on the output 32 through the OR element 14 connects the operation of the amplifier 6 at the moment when the new read information arrives at their inputs. The signal from the output of the element 46 delay through the element OR 15 (figure 1) provides the entry of the enhanced information.

0 into the register 7. At the same time, the same signal in registers 12 and 13, respectively, records the result of operation of block 10 and information obtained for recording on inputs 25. This is necessary to save the recorded information (after resetting it from inputs 25), then comparing it with the result of the operation of block 9 and the information read into register 7.

When the write-read path is working correctly, block 16, by a signal at input 36, determines the equality of the recorded and read information and does not result at the error signal output 31. If there are violations in the read / write path, then either register 7 contains information that is different from that received from inputs 25 and stored in register 13 at the moment, or the results of operation of blocks 10 and 9 differ from each other. These violations are detected by block 16 and as a failure in the device are transmitted to output 31. The operation of block 16 is gated with a signal from the {trigger} trigger 39, which is set by the signal from the output of delay element 47 and is reset when the command is received again by the signal from the output of delay element 43. As a result, the error signal at the output 31 is found all the time, starting from the moment the command ends to the next command.

In the read mode, at input 28, the device receives an address, at input 17, a command, at input 18, a strobe signal. On the Read command in register 38, a second bit is set, the unit level from whose output the AND 41 element is connected to work. The strobe signal passes through delay elements 42 Ioo43, And 41 element, delay elements 48 and 49 and forms a series of control signals reading information. The signal from output 22 gates the operation of amplifier 5 selected by decoder 8, while the input 29 selects the necessary word in drive 11, for example, from 50-53 memory slots Inputs 27 are disabled. Stored information through transistors 67 and 68 is fed to the inputs of those amplifiers 6, which are connected to work by a signal from output 33 through an element OR 14. Enhanced by information from a signal from output 35 through an element 1-ШИ 15 is entered into register 7, and then goes to output 23. At the same time, the output information is monitored by block 9, the result of which is output at output 24.

Thus, the device, when executing the Write command, analyzes the result of the recording of information, which allows, if it is unsatisfied

0

five

repeat again at the same address or select another area in drive 11 for recording.

By introducing control of the recorded and readable information in blocks 9, 10 and 16, the reliability of operation of the device is improved.

Claims (1)

Invention Formula A memory device containing a drive, read amplifiers, a control unit, an address register, an address decoder, write amplifiers, 5 input and output data registers, the information inputs of the address register and the input data register are respectively the address and information inputs of the device, the outputs of the address register are connected to the inputs of the address decoder, the outputs of the input data register are connected to the inputs of the recording amplifiers whose outputs are connected to the information inputs the accumulator, the outputs of which are connected to the inputs of the read amplifiers, is different from the fact that, in order to increase the reliability of the device, the first and second blocks are inserted into it control over oddness, control information register, buffer data register, first and second elements of LM and address signal amplifiers, moreover, one information input of the first group of comparison unit is connected to the outputs of the first odd parity control unit, whose inputs and one information input of the second group of comparison unit 0 is connected to the outputs of the output data register, whose information inputs are connected to the outputs of the read amplifiers, other information inputs of the first and second groups 5 comparison units are connected respectively to the outputs of the control information register and to the outputs of the buffer data register, whose information inputs are connected to informational 0 inputs of the input data register and inputs of the second odd-ness control unit, whose outputs are connected to the information inputs of the control data register, the output of the first element OR is connected to the control inputs of the read amplifiers, the output of the second element OR is connected to the control inputs of the control information register buffer register five data and output data register, control inputs of the input data register, address register, recording amplifiers and address signal amplifiers are connected to outputs one through four of the control blocks, the fifth and sixth outputs of which are connected to the first AND second inputs of the first OR element, first and the second inputs of the second element OR are connected to the seventh and eighth outputs of the control unit, the ninth output of which is connected to the control input of the comparison unit, the output of which is The output of the device error signal, the inputs and outputs of the address signal amplifiers are connected respectively to the outputs of the address decoder and to the address inputs of the accumulator, the outputs of the first and second odd-ness control units are the control outputs of the device, the information outputs of which are the outputs of the output data register, The input of the strobe and the inputs of the operation mode of the control unit are respectively the input of the gating and the inputs of the write-read commands of the device. / FIG. Have Editor V. Petrash Compiled by T. Zaitseva Tehred M.DNDYK Proofreader A.T.sko Order 6297/52 Circulation 588 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 J X 6B