SU1361562A1 - Device for checking time of program performance - Google Patents

Abstract

The invention relates to computing and can be used in digital computing and source systems. The purpose of the invention is to increase the efficiency of the CTR. The device contains the element OR 1, the first time counter 2, the first trigger 3, the second 4 and the third 5 time counters, the second trigger 6. The invention makes it possible to reduce the response time of the device in case of failures and faults. 1 il. dp. control / ifi Time 18s) (. Interruption (L 28sh. 00 05 shv v SP JV) ZVsh Failure siememi

Description

The invention relates to computing and can be used in digital and control systems for monitoring program execution time.

The aim of the invention is to increase the speed of control.

The drawing shows the functional diagram of the device.

The device contains the element OR 1 first time counter 2, the first trigger 3, the second time counter 4, the third time counter 5 and the second trigger 6.

The device works as follows.

To bring the device back to its original state after applying the supply voltage to the third input of the device from the monitored system, a pulse of the initial polarity setting is received, and the first counter 2 times, first 3 and second 6 trigger

A low level signal from the output of the first trigger 3 zeroed the second counter 4 times, and a low level signal from the output of the second trigger 6 zeroed the third counter 5 time a

Thus, the device is reset, and a low level signal from the outputs of the first 3 and second 6 flip-flops blocks the operation of the second 4 and third 5 time counters

During the normal course of program execution, a time interval code is periodically entered into the first counter 2 times by the information inputs, which in time slightly exceeds the execution time of the next program section. Therefore, if the programs run correctly, overflow of the first counter 2 time does not occur, since at the end of the program, the execution time of which is monitored by the first counter 2 times, it is zeroed at the zero input with a pulse. Resetting the negative polarity from the output of the element OR 1 O Pulse Reset at the output the element OR 1 is formed when a signal arrives at the fourth input of the device. The time control is reset from the monitored system.

0

five

If a violation occurs in the program executions, as a result of which the monitored section of the program does not end at a specified time interval, i.e. from the monitored system for a specified time interval signal Reset time control will not go to the fourth input

the device then overflows the time counter 2 and at its output overflow a negative polarity pulse is generated, which is fed to the first output of the device,

5 which is the output of terminating the device. With this signal, the first trigger 3 is set to a single state on a single input and enables the second counter 4 to operate.

If the monitored system responds to the Interrupt signal, the signal Reset time control from the monitored system arrives at the fourth device input in a time shorter than the time setpoint in the second counter 4 times, and the Reset signal from the element OR 1 negative polarity signal zeroes

0, the first counter 2 times and the first trigger 3. The signal from the code of the first trigger 3 zeroed the second counter 4 times. The capacity of the second time counter in advance is set to the maximum allowable system response time to the Interrupt signal. First 2, -the second 4 and third 5 time counters, when a positive voltage drop is received from the second input of the device to their counting inputs, increase their state by 1 if there is a resolution at their zero inputs. Thus, the system health check is performed.

5 interrupts of a controlled system. If the monitored system does not respond to the dodge signal for a specified period of time, i.e. Signal Reset Time Control arrives at the fourth input of the device during the time set for the second counter 4, then a negative polarity pulse is generated at its overflow output,

5 which arrives at the second device output. A negative polarity pulse from the second output of the device triggers the VC6poc / nycK signal of the monitored system.

five

0

3

By the reset / start signal, the second trigger 6 is set to a single state by a single input and a signal from its output enables the operation of the third counter 5 time. The capacity of the third time counter 5 is less than the capacity of the second 4 time counter, since the response time of the monitored system to the Reset / start signal is significantly less than the response time of the monitored system to the Interrupt signal and is set in advance to the maximum allowable system response time to the Reset / start signal.

If the monitored system responds to the Reset / Start signal, then a monitored task is restarted in the monitored system, and in response to the Reset / Start signal from the monitored system. The device’s reset signal is reset to the fourth input of the device. the

If the monitored system does not respond to the Reset / Start signal, then the Reset time control signal from the monitored system does not arrive at the fourth input of the device during the installation of the third counter 5, the third counter 5 does not zero and at the overflow output of the third counter 5 - A negative polarity pulse is generated at the third output of the device, which is the output of the System Failure.

When a negative-polarity impulse appears at the third output of the device, controller Bugnrenkova C stops ordering 6292/49

Compiled by A.Sigalov Tehred A. Kravchuk

Circulation 671 VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

615624

rollback system or its reconfiguration.

Claims (1)

Formula from obra.teni. A device for monitoring the execution time of programs, containing the first time counter and the first trigger, with the information input of the device connected to the information and input i 10 of the first time counter, the clock input of the device is connected to the counting input of the first time counter, the overflow output of which is the output violation of the operation time 15 programs of the device, with tl and h and th e with the fact that, in order to monitor the operational efficiency of the control, the element OR, the second, the trigger, the second and the third counters are entered into the device 20 time, the inputs of the initial installation and reset of the time control of the device are connected respectively to the first and second inputs of the OR element, the output of which is connected to the input of the initial setting of the first time counter and zero inputs of the first and second triggers, the clock input of the device is connected to the counting inputs of the second and third counters 30, the overflow output of the first time counter is connected to the single input of the first trigger, the direct output of which is connected to the reset input of the second time counter, output 35, the overflow of the second time counter is the output of the device's reset-start and is connected to the single input of the second trigger, the direct output of which is connected to the zero input 40 of the third counter, the overflow output of which is a system failure output. Proofreader L. Patay Subscription