SU1361509A1 - Multichannel device for programmed control of production process - Google Patents

Abstract

The invention relates to software process control, relates to advanced automation and computing technology and can be used in the organization of multiprogramming work of computers and systems, in programmable controllers, automated control systems of technological processes, machine tools with numerical control. The aim of the invention is to increase the flexibility of forming control commands. The device contains three memory blocks, a control pulse output unit, a switching unit, two comparators, two address registers, a pulse counter, a decoder, a trigger trigger, a clock generator, five AND elements, and an OR block. The invention, when used, has the positive effect of expanding the field of use by forming various lengths of control commands, as well as by reducing the required memory size based on differential storage of control command parameters. 3 hp f-ly, 5 ill. (P with O5

Description

The invention relates to industrial automation and computing technology and can be used in the organization of multiprogramming work of computers and systems, in programmable process controllers of automated process control systems, machine tools; numerical program control.

The aim of the invention is to increase the flexibility of forming control commands.

Figure 1 shows the functional diagram of a multichannel device for software control of technological processes; figure 2 is a functional diagram of the first (second) switch; FIG. 3 is a functional circuit of a switching unit; 4 is a functional block diagram of the control pulse output; figure 5 is a temporary diagram of the operation of the device. .

The multichannel device for software process control (Fig. 1) i contains the first storage unit 1, the second 2 and third 3 storage units, the first 4 and second 5 address registers, the first 6 and second 7 registers, the first 8 and second 9 switches, switching unit 10, control impulse block 11, start trigger 12, clock generator 13, pulse counter 14, decoder 15 from the first to the seventh elements AND 16-22, block of elements OR 23, information input 24 of the device, control input 25 of the device and device outputs 26.1- 26.np (where n is the number of control channels),

The first 8 (second 9) switch (figure 2) contains a decoder 27, n groups of blocks of elements And 28.1-28.p - 30.1-30, p, a group of blocks of elements OR 31.1-31.p.

Switching unit 10 (FIG. 3) contains a group of decoders 32.1-32.p, a group of blocks of elements AND 33.1-33.p, a group of elements OR 34.1-34.p.

Block 11 of the control pulses (Fig. 4) contains a block of counters 35.1-35.p, a block of elements OR 36.1-36.p, a group of blocks of elements AND 37.1-37.p, a block of elements And 38.1-38.p and an element OR 39 .

Consider the operation of a multichannel device for software control of technological processes.

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In the initial state, the memory elements of the device (with the exception of a bit. | Of the second address register defining the end of the control program) are in the zero state.

The essence of the invention is to expand the field of application of the device by extending the functionality by generating control signals with arbitrary start points and duration and by increasing the flexibility of modifying the output control sequence programs. A control pulse program is generated during a clock cycle. The control clock is divided into microtacs. The duration of control pulses is a multiple of the microtakt.

The following disciplines of impulse control are implemented in a multi-channel device for program control:

the formation of pulses is carried out in fixed micro-tacts;

generation of pulses with an arbitrary duration in fixed micro-tacts for all pulse sequences;

the formation of pulses with an arbitrary duration and an arbitrary moment of the beginning within the limits of the clock.

The multichannel device for software control of technological processes has two levels: address and operation. The address level controls the operational. In turn, in the operating level 0, control programs in the form of codes of impulse sequences are stored in two storage units for separate storage of the attributes (parameters) of the impulse moments of the beginning of the impulses and their duration. Such encoding allows to reduce the amount of memory required due to the elimination of duplicate codes. The address level storage block stores the addresses of the corresponding attributes, as well as setup codes, which allow the pulse sequence to be transmitted to the corresponding output (channel) of the device.

The operation of the device begins by submitting to the information input 24 (FIG. 1) a code defining the start address of the program of a pulse sequence. When applying sig0

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a group of elements OR 34.1-34. The switching unit 10 (Fig. 3) receives a pulse start signal. The start signals of 5 pulses in a certain micro-clock from the output of switching unit 10 open the block of elements AND 37.1 (i 1, p) of block 11 of the control pulse (). Through the appropriate block

Starting from start 25, trigger 12 is set to one state and thereby enables the generation of clock pulses from generator outputs 13. The first clock pulse from generator output 13, coming through AND 16 to the synchronous input of address 4, information from the input of elements AND 37.1 from the fields of the second register through the block of elements OR 23 of the liter 7 through the switch 9, information is transferred to the address register 4, the second clock pulse calls the storage unit 1, the information from the outputs of which 15 of the third clock pulse to the register 5 zanosits address.

Address register 5 contains five fields and a tag. The first field is re; Address Gistra 5 contains information 20; stroke) of device 26.1; secondly, the address of the next pulse sequence determines the passage of clock pulses (in the particular case it; through the element 38.1, I can subtract the initial address programs - in this case, the device operates in single-program mode). In the second 25 OR 39, a signal is generated, the resolver and the fourth field contain the receipt of clock pulses of the respected information of the second 2 and third 3 storage blocks for reading information about the code parameters of the beginning of the pulse output on the corresponding channel and the parameters of the pulse duration. The third and fifth fields are for storing setup codes. On the fourth clock pulse from the output of the generator 13 gg, the passing through them of the clock pulses through the element 19 is inverted from the outputs of the generator 13 to

the formation of the next pulse sequence. With the beginning of program execution, element 40 and 22 is opened and the subtractive inputs of counters 35.1-35.p block And pulses are received from generator 13, which change the state of the codes of the corresponding counters as the microtakt number changes. The output signal to the channel of the device 26.1 (i 1, p) is output before zeroing the corresponding counter. After zeroing the counter block 35.1-35. P a logical zero signal at the output of the element OR 39

resolves through the elements AND 16-20 the formation of a regular pulse sequence. Further, the device functions in the same way as above.

The first 8 and second 9 switches carry out a rebuilding (Fig. 2) of the code in the fields of registers 6 and 7. Such operational use of codes of one of the codes of the length of the pulses is entered into the counters 35.1-35.p that started in this microtakt. As a result, the corresponding meter counterclocker boom is different from zero and a single signal appears at the output of the OR 36.1 element. This signal, first, is output to the corresponding channel (the output of the corresponding counter 35.1 and, thirdly, at the output of the element

from the output of the generator 13 through the elements 21 and 22 to the synchronizing input of the block 11 for the issuance of control pulses. In addition, the control signal from the output of the OR element 39 of the control pulse output unit 11 (Fig. 4) is fed to the inverse inputs of the AND 16-20 elements and thus prohibits

to the storage units 2 and 3. By the first clock pulse, the information from the outputs of the storage units 2 and 3 is entered into the first 6 and second 7 registers.

According to the mark-sign of the presence of the pulse sequence of the register 6, the element 21 opens, and the pulses from the output of the generator 13 with the frequency determined by the micro-tact duration, fill the counter 14. The counter 14 together with the decoder 15 form the pulse distributor. The signals from the outputs of the decoder I5 determine the sequence (numbers) of micro-tacts and interrogate the fields of register 6 via switch 8 on switching unit 10. The fields of register 6 store the codes of the beginning of the pulses of the mapping program. If the microtakt coincides with the output of the decoder 15c by the code of the beginning of the pulse on a certain channel, at the corresponding output

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these fields followed by their use1509

a group of elements OR 34.1-34.P block.:, 10 switching (Fig. 3) appears the beginning of the pulse. The start signals of 5 pulses in a certain micro-clock from the output of switching unit 10 open the block of elements AND 37.1 (i 1, p) of block 11 of the control pulse (). Through the appropriate block

elements I 37.1 from the fields of the second register 7 through the switch 9 information

elements And 37.1 from the fields of the second register 7 through the switch 9 information

; move) the device 26.1, secondly, it resolves the passage of clock pulses; a signal is generated through the element 38.1 by subtracting OR 39; a signal is generated, allowing the clock pulses to pass through them of clock pulses from the generator outputs 13 on

The code of the pulse length codes is entered into the counters 35.1-35.p, which started in this micro-tact. As a result, the corresponding meter counterclocker boom is different from zero and a single signal appears at the output of the OR 36.1 element. First, this signal is sent to the appropriate channel (you; stroke) of device 26.1, secondly, it resolves the passage of clock pulses; And through 38.1 element by subtracting OR 39, a signal is generated that permits receipt clock pulses passing through them clock pulses from the outputs of the generator 13 to

the corresponding output of the counter 35.1 and, thirdly, the output of the element

; move) the device 26.1, secondly, it resolves the passage of clock pulses; a signal is generated through the element 38.1 by subtracting OR 39; a signal is generated, allowing the clock pulses to pass through them of clock pulses from the generator outputs 13 on

from the output of the generator 13 through the elements 21 and 22 to the synchronizing input of the block 11 of the issuance of control pulses. In addition, the control signal from the output of the OR element 39 of the control pulse output unit 11 (Fig. 4) is fed to the inverse inputs of the AND 16-20 elements and thus prohibits

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These fields, followed by their use for other channels, allows us to reduce the amount of storage units 2 and 3, and, consequently, increase the functional reliability of the device.

If it is necessary to finish the issuance of control pulses, an R-input of the trigger 12 is given a pulse through which the trigger 12 goes into the zero state, thereby prohibiting the formation of clock pulses at the outputs of the generator 12 (the zeroing circuit of the device memory elements are not shown). In addition, the end of the program of forming pulse sequences can be programmatically defined based on the task of the indication of the end of operation of the device. On this device finishes work.

Thus, a multichannel device for software control of technological processes has a more flexible organization of control commands and wide functionality, and consequently, a wider field of application due to:

forming different lengths im. pulse sequences;

forming overlapped pulse sequences;

using the same programs to follow them in any of the n channels;

ease of modification programs.

In addition, the distributed storage of pulse sequence programs reduces the amount of memory required.

Thus, for storing control programs in a known device, the required volume is determined by the expression

W,

N. p

where N is the number of pulse sequences in the i-fi program (i GGC); n is the control size

the words.

c

Moreover, n log (Y N;) + m + 1.

where m is the maximum code length of the beginning of the pulse; 1 - maximum code length of the pulse.

In general, m 1, and then there is a certain redundancy due to the presence of repetitive codes.

In this device

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N, (log (a + b) + rn-a + l b), (Ni -Illcr-);

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G-G-o V (NI -H

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the number of repeated start codes of pulses in the j-ft program; number of repeat codes

pulse lengths in the about-and program. Obviously, W, W.

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formula of invention

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1. Multichannel device for software control of technological processes, containing a storage unit, a control pulse block, an address register, first and second registers, a clock generator, an OR block, seven AND blocks, a pulse counter and a decoder, the information input of the device is connected to the first The input of the block of elements OR, the output of which is connected to the information input of the address register, the output of the register of the address is connected to the information input of the storage of the pressing block, the outputs of the output pulser The control is connected to the outputs of the device, characterized in that, in order to increase the flexibility of forming control commands, a trigger is entered into it, the second and third memory blocks, the second address register, the first and second switches and the switching block, and the output of the first memory block is connected to the information input of the second address register, the output of the first floor of which is connected to the second input of the block of OR elements, the first code of the clock generator is connected to the forward input of the first AND element, the output to torogo connected to the synchronization input of the first address register,

5, the second output of the clock pulse generator is connected to the direct input of the second element I, the output of which is connected to the control input of the first storage unit, the third output

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the clock generator is connected to the direct input of the third element I, the output of which is connected to the clock input of the second address register, the output of the second field of which is connected to the information input of the storage unit, the fourth output of the generator of clock pulses is connected to the direct input of the fourth element I whose output is connected to the control inputs of the second and third memory blocks, the fifth output

2. Device software.P.1, characterized in that the first (second) switchboard contains a decoder, n Groups of elements AND (where n is the number of outputs of the device), a group of n block elements OR, and the i-th (1 1, n a) the information input of the first (second) switch is connected to the information; the ion input of the corresponding group of blocks of elements I, the control input of the first (second) switch connected to the input of the decoder, the outputs of which are connected to

clock generator is connected to the direct input of the fifth element - the control inputs of the blocks of elements I, the output of which is connected to the sync I of the corresponding groups, the output of the 1st ronizing inputs of the first and second blocks of elements of the i of the jth group (i , j of the registers, the input of the second recording 1, p) is connected to the j-th input of the i-ro of the blocking unit connected to the information. a block of elements of the OR group, the outputs by the input of the first register, the outputs of which are connected to the outputs of the first fields of which are connected to the corresponding (second) switch, the information inputs 3, Device pop, 1, the first switch, the setting input is often that the block of which is connected to the output of the third station contains a group of decoders, the field of the second address, the output of the fourth, 25th group of blocks of elements AND, the group of which is connected to the information elements OR, and the information input of the third memory guide block, whose output is connected to the data input of the second register ,;

the outputs of the fields of the second register of the connection of the group of blocks of elements I, controlled with the corresponding information inputs of the second switch, the control input of which is connected to the output of the fifth field of the second address register, the outputs of the first switch connected to the corresponding information inputs of the switching block, the outputs of the second switch connected to relevant information

the inputs of the control pulse output block; up to control pulses contains a block

laziness, the control inputs of which are connected to the corresponding outputs of the switching unit, the output of the tag-sign of the first register is connected to the first input 4 of the sixth element And whose output is connected to the summing input of the counter and the first input of the seventh element And whose output is connected to the synchronizing input of the pulse output unit control, the control output of which is connected to the second input of the seventh element And and the inverse inputs of the first, second, third, fourth and fifth

And elements, the sixth generator output gg of the corresponding elements and clock pulses are connected to the second about the block of elements AND, and with the corresponding input of the sixth element I, - the output of the decoder is connected to the control input of the krmmut block D1I.

The outputs of the control pulse block, the control inputs of which are connected to the control inputs

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2. Device software.P.1, characterized in that the first (second switchboard contains a decoder, n Groups of elements I (where n is the number of outputs of the device), a group of n block elements OR, and the i-th (1 1, p) the information input of the first (second) switch is connected to the information; the ion input of the corresponding group of blocks of elements I, the control input of the first (second) switch connected to the input of the decoder, the outputs of which are connected to

the control inputs of the blocks of elements And the corresponding groups, the output of the 1st block of elements AND the j-th group (i, j 1, p) is connected to the j-th input of the i-ro block of the elements of the OR group, the outputs of which are connected to the outputs of the first (second switch, 3, Device pop, 1, which is different in that the switching unit contains a group of decoders, a group of blocks of elements AND, a group of elements OR, and the information inputs of the switching unit are connected to the inputs of the MSRD1PY decoders, the outputs of which are connected to the first inputs

The main input of the switching unit is connected to the second inputs of a group of blocks of elements AND whose outputs are connected to the inputs of a group of elements SH, the outputs of a group of elements of OR are connected to the outputs of the switching unit.

A. The device according to claim 1, characterized in that the block is

counters, block of elements AND, block of elements SHS, group of blocks of elements AND, element OR, and the information inputs of the block of pulses

control units are connected to the information inputs of the corresponding blocks of elements AND groups, the outputs of which are connected to the information inputs of the corresponding block counters

counters, single outputs of which are connected to the inputs of the corresponding elements of the NL of the block of elements. OR, the outputs of which are connected to the inputs of the SHSh element, with the first inputs of the corresponding elements AND of the block of AND elements and with the corresponding

The outputs of the control pulse block, the control inputs of which are connected to the control inputs

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corresponding blocks of elements Yenas with subtractive inputs of the corresponding group, synchronizing input of the block of forward counters of the block of counters;

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Compiled by I.Shvets Editor A.Vorsvich Tehred L, Serdyukova

Order 6281/46 Circulation 863 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d.A / 5

Production and printing company, Uzhgorod, Projecto st., 4

Proofreader L. Pilipenko

Claims (6)

device for software control of technological processes, containing a storage unit, a unit for issuing control pulses, an address register, first and second registers, a clock pulse generator, an OR block, seven AND elements, a pulse counter and a decoder, the information input of the device is connected to the first input of the element block OR, the output of which is connected to the information input of the address register, the output of the address register is connected to the information input of the storage unit, the outputs of the pulse control unit are connected are connected to the device outputs, characterized in that, in order to increase the flexibility of generating control commands, a trigger is introduced into it, a second and third memory blocks, a second address register, first and second switches and a switching unit 45, the output of the first memory block being connected to information input of the second register ad1. Multichannel where N is the number of pulse sequences in the i-th program (i = GG ”k); p _t - bit depth of the control word. to Moreover, n _T = J log ₂ (N;) Г + ш + 1, where ш is the maximum length of the code for the beginning of the pulse; 1 - the maximum length of the pulse width code. race, the output of the first field of which is connected to the second input of the element block 50 to OR, the first output of the clock generator is connected to the direct input of the first AND element, the output of which is connected to the clock input of the first address register, 55 the second output of the clock ^- pulse generator ^is connected to the direct input of the second element And, the output of which is connected to the control input of the first storage unit, the third output • 7 of the clock generator is connected to the direct input of the third element And, the output of which is connected to the clock input of the second address register, the output of the second field of which is connected to the information input of the storage unit, the fourth output of the clock generator is connected to the direct input of the fourth element And, the output of which is connected to the control clock generator vlyayuschimi inputs of the second and third storage units, a fifth output is connected to the direct input of the fifth AND gate, whose output is connected with the clock inputs of said first and second registers, the output of the second storage unit connected to the information 2. The device according to claim 1, characterized in that the first (second) switch contains a decoder, η ι groups of AND elements (where η is the number of device outputs), a group of η blocks of OR elements, the i-th one (i = 1 , η) the information input of the first (second) switch is connected 10 ^{with the} information input of the corresponding group of blocks of elements AND, the control input of the first (second) switch is connected to the input of the decoder, the outputs of which are connected to 15 control inputs of blocks of elements And the corresponding groups, the output of the i-ro block of elements And the j-th group (i, j = 1, η) is connected to the j-th input of i-ro. a block of elements OR groups, outputs by the first input of the first register, the outputs of the first fields of which are connected to the corresponding information inputs of the first switch, the settings input of which is connected to the output of the third field of the second address, the output of the fourth 25 fields which is connected to the information input of the third storage unit, the output which is connected to the information input of the second register: the outputs of the fields of the second register are connected to 30 corresponding information inputs of the second switch, the control input of which it is single with the output of the fifth field of the second address register, the outputs of the first switch _Z d are connected to the corresponding information inputs of the switching unit, the outputs of the second switch are connected to the corresponding information inputs of the output pulse control unit, the control inputs of which are connected to the corresponding outputs of the switching unit, the output label of the first register is connected to the first input of the sixth element And, dd the output of which is connected to the summing input of the counter and the first input of the seventh element And, you the course of which is connected to the synchronizing input of which is connected to the outputs of the first (second) switch. 3. The device according to claim 1, characterized in that the switching unit comprises a group of decoders, a group of blocks of AND elements, a group of OR elements, and ° the information inputs of the switching unit are connected to the inputs of the group of decoders, the outputs of which are connected to the first inputs of the group of blocks of AND elements, the control input of the switching unit is connected to the second inputs of the group of blocks of AND elements, the outputs of which are connected to the inputs of the group of OR elements, the outputs of the group of OR elements are connected to the outputs of the switching unit. I 4. The device according to claim 1, characterized in that the control pulse output unit comprises a counter unit, an AND element block, an OR element block, an AND element block group, an OR element, the information inputs of the control pulse issuing block being connected to the information inputs of the respective element blocks And the groups whose outputs are connected to the information inputs of the respective counters of the control pulse issuing unit, the control output of which is connected to the second input of the seventh AND element and the inverse inputs of the first, toro-, second, third, fourth and fifth AND gates, the sixth clock pulse generator output is connected to the second input of the sixth AND gate, - the output of the decoder is connected to the control input of the switching unit. 5Q counters whose single outputs are connected to the inputs of the corresponding elements OR block of elements. OR, the outputs of which are connected to the inputs of the element OR, with the first inputs of the corresponding elements AND about the block of elements AND and with the corresponding outputs of the block issuing control pulses, the control inputs of which are connected to the control inputs 9 1361509 10 corresponding blocks of elements And yen with subtracting inputs of the corresponding group, the synchronizing input of the block of issuing control pulses is connected to the second inputs of the elements And block of elements And, the outputs of which are connected to the counters of the counter block, the output of the OR element is connected to the control output of the block of issuing control pulses.