SU1352452A1 - Extreme regulation system - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to automatically adjust the power modes of optically controlled transponders in optical and optoelectronic information processing systems. The purpose of the invention is to increase speed, accuracy, which is achieved by implementing an almost instantaneous return to a global extremum point and subsequent adjustment with a given accuracy to a global extremum. The extremal control system contains a clock impulse generator, two frequency dividers, three keys, seven AND elements, five IL elements, two counters, three digital-to-analog converters, a voltage-to-frequency converter, an amplitude modulator, a control object, a differential sensor, two differential amplifiers, two NAND units, inverter unit, two triggers, algebraic summing unit, two memory registers, four analog comparators, peak detector, analog-to-digital converter, operas tive memory, digital komparator-, monostable, two Dih differentiate and attenuator element. 3 il. with s

Description

The invention relates to automation and computer technology and can be used to automatically adjust the power modes of optically controlled transponders.

The purpose of the invention is to increase speed and accuracy by implementing an almost instantaneous return to the global extremum point, taking into account the inertia of the measurement and conversion channel, both in the search mode and in the mode of adjustment to the global extremum.

FIG. Figure 1 shows a structural electrical circuit of an extreme control system; in fig. 2 and 3 - time diagrams of his work.

The system of extreme control contains a generator of 1 clock pulses (GTI), the first 2 and second 3 frequency dividers, the first key 4 the first 5 and the second 6 elements AND, the first 7 and second 8 elements OR, the first 9 and second 10 counters, the first 11 and the second 12 digital-to-analog converters (D / A converters), voltage-to-frequency converter 13, amplitude modulator 14, control object 15, yes-differential sensor 16, first differential amplifier 17, first AND-NE element 18, inverter unit 19, third element OR 20, the second element AND-NOT 21, the first trigger 22, che Werth OR gate 23, the block 24 algebra rj sequence unit 24 connected alge-. summation, the first 25 registers, the first re- and second 26 memory registers, the first hist 25 memory and the first switch 27 and the second 28 switches, the third 27. Between the outputs of the second counter, And 29, the second trigger 30, the first 10 and its installation inputs include a differentiating element 31, the first 40 serially connected second out 32 and second 33 blocks of sampling-storage 26 of the memory and the second switch

The second differential amplifier 34, the first 35, the second 36 and the third 37 analog comparators, the fourth 38 and five 39 elements AND, the fifth element OR 40, the third 41 and fourth 42 switches, the sixth 43 and the seventh 44 elements AND, the peak detector 45, analog-to-digital converter (DAC) 46, random access memory (RAM) 47, digital comparator 48, second 49 and third 50 keys, one-shot 51, third-DAC 52, attenuator 53, quarter analog comparator 54, second differentiating element 55 and sixth element OR 56.

GTI 1 is connected in series with dividers 2 and 3 frequencies, the first

key 4 - with the second element AND 6 and with the first element OR 7, the output of which is connected to the summing input of the first counter 9. Between the output of the first key 4 and the subtraction input of the first counter 9, connected in series are the third element AND 29 and the second element OR 8,

the input of the first key 4 is connected to the output of the GTI 1. The first counter 9 is connected in series with the first. D / A converter 11, voltage-to-frequency converter 13, amplitude modulator 15 control. Between the outputs of the first counter 9 and the counting input of the second counter 10 are connected in series the first element NAND 18, the second trigger 30 and the third element OR 20. Between the outputs of the first counter 9 and the second input of the second trigger 30 are connected the series-connected inverter unit 19, the second element AND-NOT 21 and

the fourth element OR 23. The inverse output of the second trigger 30 is connected to

The second input of the third element OR 29 and the second input of the third element And 29, the second input of the second element And 6 is connected to the output of the second trigger 30 and the input for setting the sign of the block 24 of algebraic summation. Between the outputs of the first counter 9 and its installation inputs are turned on after the torus 28. The outputs of the second counter 10 and the interconnected write enable inputs of counters g 9 and 10 and the control inputs of the switches 27 and 28 are connected in series with the first element And 5, the first trigger 22 and the first differentiating element 31. Differential sensor 14 is connected in series with the first differential amplifier 17 by the first sampling-storage unit 32, the second analog Comparator 36, the sixth element AND 43 and the fifth element OR 40, Exit is connected to the control input of the third switch 41 having inputs connected to the input and output of the first frequency divider 2 sootvetstven0

but. The input of the fourth switch 42 is connected to the output of the third switch 41, and the first and second outputs are connected to the second inputs of the fourth and fifth elements AND 38 and 39, respectively, the outputs of which are connected to the second inputs of the elements OR 7 and 8, respectively. A second block 33 for sampling and storage is connected between the output of the first differential amplifier 17 and the second input of the second differential amplifier 34. The third analog comparator 37 is connected between the output of the second differential amplifier 34 and the second input of the seventh element 44, the output of which is connected to the second input of the second the element OR 40, the direct output of the second divide- ting frequency 3 is connected to the reference input of the first block 32 of the sample-storage and the first input of the seventh element AND 44, the inverse output of the second frequency divider 3 is connected to the reference the second input of the sixth element And 43, the peak detector 45 is connected in series with the A / D converter 46, the RAM 47, the digital comparator 48 and the second switch 49, the output of which is connected to the input controlling the third key 50, the output of which is connected to the write enable input of the RAM 47 and memory registers 25 and 26. The first analog comparator 35 is successively connected to the one-oscillator 51 and the third key 50. The second input of the first analog comparator 35 is connected to the output of the peak detector 45, and the first input to the input of the peak detector 45 and the output of the first differential amplifier 17. the digital comparator 48 inputs are connected to the A / D converters 46, the third CAC 52 is sequentially connected to the attenuator 53, the fourth analog comparator 54, the second differentiating element 55 and the sixth element OR 56, the second input of which is an external input th reset, and taken the analysis is connected to the reset bus. The second input of the fourth analog comparator 54 is connected to the output of the peak detector 45. The output of the first trigger 22 is connected to the control input of the second key 49 and the gate input of the fourth comparator, the GTI output 1 is connected to the second input of the one-vibrator 51, the inputs to the O counters 9 and 10 peak detector 45, RAM 47, memory registers 25 and 26, the first trigger 22 and the second input of the fourth OR element 23 are combined and are the system reset bus, and the sign setting input of the algebraic sum block 24 is connected to the forward output of the driver. cerned trigger 30.

GTI 1 can be performed according to any well-known scheme, for example, on two logical elements 2I-NOT. Dividers 2 and 3 frequencies can be executed on Ili triggers on counters' microcircuits, for example 133NE5; counters 9 and 10 - on the corresponding chips, for example 133IE7 and 133IE5; the first, the second and third DACs are on 594PA1 chips; ADC 46 - on the 592PV1A microcircuit; one-shot 51 - on the counter with a decoder at the output (element I); digital comparator 48 - on a microcircuit 533SP1; analog comparators 35, 36, 37 and 38 - on micro-circuits 521SA4; algebraic summing unit 24 — on 555MIC chips and 530KP14 switches with preliminary calculation of the binary addition of the subtracted number.

FIG. 2a-e depict voltage plots at the outputs of the GTI 1, the first 2 and second 3 frequency dividers, the first output of the fourth switch 42, the second output of the fourth switch 42, and the output of the second analog comparator 36, respectively.

FIG. Za-e depicts the processes of tuning the system to the top of the global extremum at times t0; tg-t, and, o.

The system of extreme regulation works as follows.

On a command from an external device arriving at the second input of the sixth element OR 56, counters 9 and 10, memory registers 25 and 26, peak detector 45 and RAM 47 are zeroed out, and the first and second triggers 22 and 30 are converted to the state in which the logic levels from their outputs permit the signal to pass through the second element 6 and the prohibition to pass the signal through the third element 29 translates the first key 4 into a closed state.

they prohibit the signal from passing through elements 38 and 39, switch key 49 into a closed state and block the operation of the fourth analog comparator 54. GTI pulses 1 through the first key 4, second element 5 and the first element OR 7 begin to flow to the summing input the first counter 9. The output of the first DAC 11 begins to form a stepwise increase in voltage, which is converted into a proportionally increasing value of the frequency in the converter 16. The voltage of the increasing frequency is amplified by the amplitude modulator 14 and the output It is supplied to the power inputs of the control object 15. When the first counter 9 is filled up to a certain value, less than the maximum possible, and equal to 2π (where n is the number of bits of the first counter 9), at the output of the first element NAND 18 connected to the outputs of the corresponding bits of the first counter 9 and performing the function of the decoder, an O - 1 differential is formulated, which pushes the second trigger 30 to another steady state. In this case, the second element And 5 receives a ban (0) on the passage of the signal, and the third element And 29 - permission (1). The GTI pulses 1 begin to flow into the subtraction input of the first counter 9. At the same time, the pulse from the output of the third element OR 23 begins to fill the second counter 10. At the output of the first DAC 11, a step-down voltage is formed, which is transformed into a proportionally decreasing frequency value a voltage to frequency converter 16. The transmission coefficient of the amplitude modulator 14 is changed by the second

DAC 12 on the value of y p (where n is the number of bits of the second counter 10). When the content of the first counter 9 decreases to a value greater than the value equal to zero, an output O - 1 is formed at the output of the second element NAND 21, which transfers the second trigger 30 to a new stable position. The second element And 6 begins to pass pulses from the output of the GTI 1, and the third element And 29 - not to miss them. So, on you -

ten

20

25

3524526.

During the first DAC 11, a triangular voltage is formed, and at the output of the second DAL 12 - linearly increasing. In this case, the variation of independent variables — frequency and amplitude — is performed in the entire volume of the state space of the object being controlled.

Blocks 45-51 and 35 measure and store extreme states of the control object 15 as follows.

The signal, whose amplitude is proportional to the quality of the state of the object 15, from the output of the differential sensor 16 is fed through the first differential amplifier 17 to the input of the peak detector 45. The peak detector 45 remembers the maximum signal and begins to discharge (slowly compared to charge) . A / D converter 46 converts the voltage stored by the peak detector 45 into a code. The voltage at the second input of the digital comparator 48 is greater than the first.

A digital comparator (by appropriately decrypting the outputs of the 533SP1 chip) works if the code value of the signal at its first input is less than at the second one. In this case, the third key 50 is transferred to the closed state. Thus, the digital comparator 48 is triggered and the pulse generated by the single-oscillator 51 records the value of the signal from the output of the A / D converter 46 into RAM 47 via the third key 50. In this case, the digital comparator 48 returns to its original position, since the value of the codes is its inputs are equal. If the value of the extreme value of the signal recorded in the code is followed by a larger value, the process is repeated. If the value of the extreme value recorded in the code is followed by a lower extreme value, the first analog compara-. The torus 35 triggers and starts a single vibrator 51. However, the pulse from the output of the one-shot 51 does not pass to the RAM recording resolution input, since the third key 50 remains in the open state, because the code value at the second input of the digital comparator 48 is less than the first. The memory size of RAM 47 is minimal, since one value is written to it, i.e. global extremum, and the preceding ones are erased.

thirty

35

40

45

50

55

The peak detector 45 seems to stretch the extreme value of the signal in time, as a result of which the performance requirements of the A / D converter 46 are many times lower, which makes it possible to use an ADC approachron, i.e. with the number of bits greater than or equal to 12, and, therefore, to obtain high accuracy.

With the passage of extremal, increasing in magnitude values, the write pulse coming from the output of the one-shot 51 to the enable input

RAM 47 records are simultaneously received by the J5 ramp of extreme characteristic and to the write enable inputs of memory registers 25 and 26. In this case, the frequency and amplitude codes corresponding to the extreme value of the signal are recorded in these registers. How much a pulse at the output of the one-shot 51 is formed after a specified time by counting a certain number of pulses from the output of the GTI 1,

arriving at his second entrance. This is 25 liters 34. Since before this was included the number of pulses converted into a code is subtracted from the code at the output of the first counter 9, taking into account the sign, which is determined by the state at the output of the second trigger 30 with the goal of returning to One of the objects of the regulation 15 to reach the top of the global extremum, taking into account the inertia of the ADC 46 and the one-shot 51 (Fig. 3).

Return is almost instantaneous as follows.

When a first flip-flop 22 is thrown, a pulse is generated at the output of the first differentiated-40 circuit 31 that switches the switches 27 and 28 to a position where the signal codes from the second sampling-storage unit 33 are subtracted, then at the first time tg (pulse in Fig. 2d and point a in Fig. 3a) the voltage at the inputs of the second differential amplifier 34 are equal to each other. In this case, the switches 41 and 42 are in the initial state (Fig. 1), the pulses from the output of the second frequency divider 3 (Fig. 2c) hold the fourth switch 42 in each state for a time

T

 (where T is the period of the signal from the outputs

second divider 3 frequencies).

Thus, the first pulse a passes from the output of the second frequency divider 2 through the switches 41 and 42 to the input of the summation of the first counter 9 and increases the frequency of the signal of the strokes of the first and second registers 25 to 45 from the output of the converter 13. At the same time, 26 memories. At the same time, the same voltage increases. The voltage at the outputs of the pulse is fed to the inputs of the installation of differential amplifiers 17 and 34 counters 9 and 10. At the same time, in the counter (Fig. Pro, point c). The second impulse b ki 9 and 10 records codes (Fig. 2d), passes the same circuit, another signal from the outputs of registers 25 and 26, 50. More increases the voltage at the outputs of differential amplifiers 17 and 34 (Fig. Pro, point c ). The threshold for triggering the second analog comparator 36 (tj,

and the values of the voltage of the signals corresponding to the global extremum are formed at the outputs of the GEL 11 and 12. If the return to the state space point is inaccurate or 55 of FIG. 2e), in which the threshold is positive for the time of studying and measuring the pair (in the third analog comparator of the object 15 of the control of the generator 37, the threshold is negative (Fig. 3a), it was changed, or one of the external non- through the sixth

dependent variables (e.g., light intensity) began to change, the system automatically adjusts to the top of the global extremum as follows.

With the above switching of the first trigger 22, the signal from its output turns off the first key 4 and gives permission to pass signals from the outputs of the fourth switch to the inputs of summation and subtraction of the first counter 9 (Fig. 2),

Suppose that in the initial position, the operating point was on the curve (Fig. Za, point i), and the voltage at the direct output of divider 3 frequencies at THIS point in time is 1 (Fig. 2c). This causes the first sampling-storage unit 32 to open and the voltage from the output of the first differential amplifier 17 to the non-inverting input of the second differential amplifier, the second sampling-storage unit 33, then at the first time point tg (pulse in Fig. 2d and point and in Fig. 3a), the voltage at the inputs of the second differential amplifier 34 is equal to each other. In this case, the switches 41 and 42 are in the initial state (Fig. 1), the pulses from the output of the second frequency divider 3 (Fig. 2c) hold the fourth switch 42 in each state for a time

T

 (where T is the period of the signal from the outputs

the element AND 43 and the fifth element OR 40 translates the third switch 41 into a field, in which high-frequency pulses pass through it directly from the GTI output to the summing input of the first counter 9 (Fig. 2d — pulses a, b, c, d, e , f ,, g, h, i). After the arrival of the ninth pulse i, the state of the outputs of the second divider 3 frequency changes (Fig. 2c, t, Fig. 2e). The fourth switch 42 enters a state where its output is connected to the subtraction input of the first counter 9. The second sampling-storage unit 33 is turned on. Since, at the same time, the inputs of the differential amplifier 34 are equal, the comparator 36 releases and the third switch 41 returns to the initial state. Pulses a, b, c (fig. 2d) increase the voltage at the inverting input of the second differential amplifier 34 with respect to the non-inverting input; Again, the comparator 36 (t, Fig. 2e) is triggered, however, the voltage 1 from its output does not pass to the control input of the third switch 41 j since, at this time, the voltage at the second input of the sixth element And 43 is equal to O (Fig. 2c). Thus, the frequency of the transducer 13 is reduced only by three steps a, b, c (Fig. 36). Then, the first sampling-storage unit 32 (t, Fig. 2e) is re-enabled, and movement to the top of the extremal characteristic occurs again (Fig. 3c). However, the number of steps of movement is less, since when approaching the apex, the gradient of change of function decreases, and consequently, more movements are needed to exceed the threshold by running the comparator (Fig. 2d, e, fig. Sv). Then the process is repeated until the top of the extremal characteristic is reached (Fig. 3, g).

If the operating point were on the right side of the ramp of extreme characteristics, the process would be similar, with the only difference that the third analog comparator 37 would work, not the second. Similarly, the adjustment process occurs if at the moment of adjustment the first counter 9 rendered

with on the negative slope of the formed triangular voltage.

The use of an automatic substring of the power supply modes of the control object in combination with the use of sampling-storage units reduces the response speed with absolute stability, since feedback during the adjustment in the control loop is broken and, as a result, makes it possible for the optical information processing system to function when the illumination changes rapidly , In this mode, the tuning system can function for a long time. If, for some reason, the magnitude of the global extremum has decreased by an amount greater than the threshold of the four-way analog comparator 54 specified by attenuator 53, i.e. the voltage at the output of the peak detector 45 has decreased to a predetermined value, the comparator 54 is triggered, the pulse from the output of the second differentiating circuit 55 brings the system to the initial state and the process repeats.

When forming a triangular voltage from the output of the first DAC 11, not all bits from the outputs of the first counter 9 are used in order to provide adjustment stocks if the global extremum point of the output function of the control object 15 is in the region close to the vertices of the triangular oscillation. In this case, with adjustment, a margin of frequency variation is provided.

The technical advantage of the invention lies in the realization of an almost instantaneous return to the space of the states of the object of regulation after studying all of its possible states by varying the independent variables, in increasing

the accuracy of adjustment as a result of taking into account the inertia of the system for measuring the point corresponding to the global extremum when the system returns to this point after studying the state space of the controlled object, as well as in ensuring the possibility of adjusting the system after tuning to the global extremum.

Claims (1)

Invention Formula An extremal control system containing a clock pulse generator connected to the input of the first key, the first counter, the output of which is connected via a serially connected digital-to-analog converter, a voltage-to-frequency converter and an amplitude modulator connected to the input of the control object. which is connected a differential sensor connected via a series-connected first differential amplifier, a peak detector and an analog-to-digital converter with a random access memory input, the outputs of which are connected to the first inputs of a digital comparator, the output of which is through the second key connected to the control input of the third key the first differential amplifier is connected to the first input of the first analog comparator, the second input of which is connected to the output of the peak detector, output The first analog comparator is connected through a serially connected one-shot and a third key to the recording resolution of the random access memory, whose inputs are connected to the second inputs of the digital comparator, and also contains a second counter, the output of which is connected to the amplitude modulator control input through the second diffraction converter. and through the first element And to the input of the first trigger, the installation inputs in O of the peak detector of the first and second counters, the first trigger and the operative A storage device is connected to the reset bus, characterized in that, in order to increase the speed and accuracy of the system, AND, five elements OR, two AND-NOT elements, second trigger, inverter unit, an algebraic sum block, two memory registers, four switches, two differentiating elements, two frequency dividers, two sample-storage blocks, a second differential amplifier, second to fourth analog comparators, second and third digital-to-analog converters, and a shunt, the first inputs of the second and third elements AND are connected to the output of the first key, the outputs of the second and third elements AND are connected respectively to the first - inputs of the first and second elements of the RShI, whose outputs are connected respectively to the summation and subtraction inputs of the first counter, the outputs of which are - are connected to the inputs of the first NAND element. block inverters and block alge-. Brain summing, whose outputs through the first memory register are connected to the inputs of the first switch, the output of which is connected to the installation inputs of the first counter, the output of the first differential amplifier is connected to the inputs of the second differential amplifier through the first and second sampling-storage units . The second and third comparators, the output of the first element is NOT connected to the first input of the second trigger, the direct output of which is connected to the first input of the third element OR, the second input of the second element AND and the input of the sign installation of the algebraic sum block, the second input of which is correction, the outputs of the inverter unit through the second element AND-NOT connected to the first input of the fourth element OR, the output of which is connected to the second input of the second trigger, the inverse output of which is connected to the second inputs of the third the AND element and the third OR element, the output of which is connected to the counting input of the second counter, the output of which through the second memory register is connected to the first group of inputs of the second commutator, the output of which is connected to the installation inputs of the second counter, the output of the first trigger is connected to the first inputs the fourth and fifth elements And, with the control inputs of the first and second keys, the gate input of the fourth comparator and the input of the first differentiating element, the output of which is connected to the input w of the recording resolution of the first and the second counters and control inputs of the first and second switches, the second group of inputs — which are connected to the common bus of the device; the output of the clock generator is connected to the input of the first frequency divider, the first input of the third switch, the second input one-shot, the output of the first frequency splitter is connected to the input of the second frequency splitter and the second input of the third switch, the output of which is connected to the input of the fourth switch, the first and second outputs of which are connected to the second inputs of the fourth and fifth And elements, the outputs of which are connected to the second inputs the first and second elements OR, respectively, the direct output of the second frequency divider is connected to the first input of the sixth element AND, the input of the control, the fourth commentator and the reference input of the first sampling unit EIW inverted output of the second frequency divider is connected to the first input of the seventh AND gate, and the reference input of the second y-sampling-storage unit outputs the second and third anal Ogove, comparators respectively connected to the inputs Auto rymi sixth and seventh AND gates whose outputs via the fifth element OR is connected to the control input of the third switch; the output of a random access memory is connected via serially connected digital-analog converter and attenuator to the first input of the fourth analog comparator, in the second input of which is connected to the output of the peak detector, the output of the fourth analog comparator is connected to the second differentiating element the first input of the sixth IL element, the second input of which is an external reset input, the output of the sixth element OR ene an external bus reset, write enable input of the first register and second memory connected to the output of the third switch, and the installation in entrances On the first and second memory registers and a second input connected to the fourth OR k etementa bus reset. tv) ““ 0) and ABOUT) 0} fie.d