SU1352408A1 - Device for measuring amplitude and phase of signals of phased array radiators - Google Patents

Abstract

The invention provides improved performance. The device contains a microwave generator 1, a probe 2, a controlled phased antenna array, (PAR) 3, control unit 8, multi-tap delay line (MLS) 9, inverters 10, adders 11,12, signal extraction unit 13, block 14 control and recording and pulse meters 15. HEADLAY 3 consists of N emitters 4, N phase shifters (EF) 5, frequency conversion unit 6 and adder 7. The test signal of generator 1 is received by emitters 4 of the controlled EAR 3 and through EF 5 enters block 6 The control unit 8 controls the FS 5, that is, that the phase P of the passing signals Change is simultaneously at a frequency of I SI. once per time equal to the measurement period of the amplitude and phase of the signals of P. emitters 4. The control sequence of jx groups of emitters 4 (j N / P, where P is the number of simultaneously controlled emitters 4) installs block 14. After conversion in block 6 and summation in the adder 7 signals from PAR 3 are sent to the MLS 9 and further to the adders 11,12. The adder 11 extracts the signal generated by switching the phases of the PV 5, and the adder 12 the signal of the detected PAR 3 (reference signal). The measured values of the P signal parameters are received in block 14, in which, after the end of the measurement, the values of the amplitude-phase distribution over the PAR emitters 3 will be stored. 2 Cp. f-ly, 6 ill. S (L with SP o 4 O 00 ipael

Description

The invention relates to a technique of antenna measurements and can be used to measure the amplitude and phase of the signals of emitters of phased antenna arrays.

The aim of the invention is to increase speed.

FIG. Figure 1 shows the structural electrical circuit of the device for measuring the amplitude and phase of the signals of the emitters of a phased antenna array; in fig. 2 is a functional diagram of a frequency conversion unit;

Fig. 3 is a functional block diagram of the 15 received by P controlled elucidation controls; in fig. 4 - by the functionals 4 of the HEADLAMP 3, the simultaneous allocation circuit of the allocation unit is signalized by the value of J cf, and with a frequency Л „times during the time t equal to the measurement period of the amplitude and phase of the signals

fishing; in fig. 5 is a functional diagram of the control and registration unit;

than magnitude

remains constant n25

NOI for discrete time

.t; -2i;

n is even in FIG. 6 - functional diagram of a block-20 p controlled emitters 4. Synchronization.

The device for measuring the amplitude and phase of the signals of the emitters of the HEADLIGHTS contains a microwave generator 1, a probe 2, a controlled phased antenna array (PAA) 3 consisting of N emitters 4, N phase shifters 5, a frequency conversion unit 6 and a sum of a generator 7, block 8 control, multi-line delay line 9, inverters, 10, first 11 and second 12 adders, signal extraction unit 13, control and recording unit 14, pulse meters 15.

The frequency conversion unit 6 (Fig. 2) has an input t2N of the keys 16 .and 17, N of the frequency mixers 18.

The block 8 control (fig.Z) includes two registers 19 and 20

thirty

where Z, t; - t,

nth integer.

- 1 ..., p, S 2Tif „

35

When the generator 1 operates in a pulsed mode, the duration of the emitted pulse i is chosen from the condition

t: t

where n is an even integer.

The sequence of control j-x groups of emitters 4 (j 1 ... N / P,

shift, 2mN logic elements And 21 and 22, two delay lines 23 and 24, two memory blocks 25 and 26, mN keys 27, a decoder 28, four gates 29-32.

The block 13 of the signal allocation (Fig. 4) includes P + 1 filters 33 and 34, 2P-1 mixers 35 and 36, two generators 37 and 38, and P-2 frequency multipliers 39.

The composition of the control and recording unit 14 (Fig. 5) includes an electronic computer 40, a synchronization unit 41, P computer communication elements with a digital measuring device 42.

The synchronization unit 41 (FIG. 6) includes two decoders 43 and

44, four logical elements And 45-48, four shapers 49-52 them

pulses, generator 53 clock pulses, RS flip-flop 54, three delay lines 55-57, three inverters 58-60, three valves 61-63.

The device (figure 1) works as follows.

The ultra high frequency (UHF) test signal from the generator 1 at the top frequency is emitted by probe 2 and received by the radiators 4 of the controlled PAR, 3, the phase shifters 5 of which are controlled by the control unit 8 in such a way that the signals phase.

received by the P controlled emitters 4 PAR, 3 varies simultaneously

variable J cf, and with a frequency Л „times during time t, equal to the measurement period of the amplitude and phase of the signals

than magnitude

remains constant n controlled emitters 4. When-

NOI for discrete time

25

.t; -2i;

n - even

where Z, t; - t,

nth integer.

- 1 ..., p, S 2Tif „

When the generator 1 operates in a pulsed mode, the duration of the emitted pulse i is chosen from the condition

35

t: t

where n is an even integer.

The sequence of control j-x groups of emitters 4 (j 1 ... N / P,

where P is the number of simultaneously controlled emitters 4 included in each group) is installed by control and registration unit 14, the outputs of which are connected to the inputs of control unit 8.

The signals from the N phase shifters 5 of the controlled PAR 3 are supplied to the N respective inputs of the first group of inputs of the conversion unit 6 frequently. phAR 3. In block 6 of the frequency conversion, the frequency of the WP signals P of the monitored emitters of the 4th j group is converted to the corresponding

Wnp +

five

Wnp WQUJi U)

kwp where

/ 0.,

 R

Etc

current frequencies k 1 ... P;

 c (c is any positive integer). For this purpose, the N / P inputs of the second group of block 6 are supplied with control signals from the corresponding N / P

the outputs of the control unit 8, and the P inputs of the third group of block 6 are harmonic oscillations with frequencies and - - 1 holes (1 0.1, .., Р-1) from the corresponding P outputs of the first group of the signal extracting unit 13. From the N outputs of block 6, the signals are fed to the N corresponding inputs of the adder 7 of the HEADLAMP 3, from the outputs of which the total signal from the N emitters is fed to the input of the multi-drop line (MLS) 9 with N taps. Delay time t

SCA

between

adjacent taps equal to the switching period P of the monitored phase shifters 5 of the PAR 3 and are selected from the frequency ratio (c + k) u; p frequency 2L, and the number of taps is the number of switching (switching) P of the monitored phase shifters 5 during the measurement period of the amplitude and phase of the signals received P controlled emitters, i.e.

TG (c + k) wp

 C Ll

where c, is any integer; N p.

From the outputs of the MLS signals and the corresponding inputs of the adders 11 and 12, and each even branch of the MLS 9 is connected to the input of the adder 11 through one of the inverters 10.

Let N p, n be an even integer, F the signals at the output of the controlled i-ro radiator, respectively, with 4C | O,, F. -, the signal at the output of each i-ro uncontrolled radiator, respectively, with A (0. Then, at the output of the adder 11, all signals 2 are in phase and out of phase — F, i.e. the signal generated by phase switching controlled phase

2Q are harmonic oscillations at frequency a) on. the first inputs of the keys 16 and 17 of the corresponding channels. From output A, a control signal is applied to the second inputs of keys 16 and 17 of the first group of P channels, while the keys 17 of the first group of P channels are closed, and the keys 16 are opened. Therefore, harmonics with frequency u) o are fed to the first inputs of mixers 18 of the first group R of channels, and harmonics with frequencies WT- - e Fr (e 0.1 ,. .. P-1). From the outputs

Spinner F. At the output of the adder of mixers 18 of the first group P of the channel-12, on the contrary, F is added in phase, harmonic oscillations Fj are out of phase, and the signal of the controlled PAR, called reference (F), is output. When summing increments, the accuracy increases from 50

with frequencies (c + k) u) p (k 1,2, ... P) to outputs c ... from block 6. At inputs A2 ... block 6 there are no control signals, therefore the keys of 17 other channel groups the keys 16 are closed, so the harmonic oscillations at the frequency w are removed from the outputs of these channels. To measure the parameters of the signals of the second group of channels, it is necessary to send a control signal from the input A /; block 6 to the second inputs of keys 16 and 17, the third group - from the entrance A, etc.

measurements by reducing the fast-changing phase instability of the signals F, and Fj compared to F and F, while

 (N-P) NiN

I

n.

H;

from the output of the adder 11, the signals F j (k 1 ...) with frequencies (c + k) ujp are fed to the first input of the block 13, to the second input of which the reference signal F is fed. In block 13, the frequency separation of signals occurs first.

F, and then convert each of the signals to the frequency and. From the P outputs of the second group of block 13, the signals at frequency ы are fed to the first inputs P of the corresponding pulse meters 15, to the third inputs of which the reference signal F is fed. Measurement of the parameters P of the signals F by pulsed meters 15 is carried out only when their second signals the inputs come from the first output of block 14, a signal that coincides in time with the discrete tj (tf nt,), where n is an even integer number). The amplitude and phase values of the measured P signals in a binary-decimal code are supplied to the control unit 14, in which, after the measurement process is completed, the values of the amplitude-phase distribution over the Emitters 4 of the HEADON under test are stored.

The frequency conversion unit 6 (Fig. 2) operates as follows.

d

With exits with,

, Wed ... S |., .. g, C |

Q is given harmonic oscillations at frequency a) on. the first inputs of the keys 16 and 17 of the corresponding channels. From output A, a control signal is applied to the second inputs of keys 16 and 17 of the first group of P channels, while the keys 17 of the first group of P channels are closed, and the keys 16 are opened. Therefore, harmonics with frequency u) o are fed to the first inputs of mixers 18 of the first group R of channels, and harmonics with frequencies WT- - e Fr (e 0.1 ,. .. P-1). From the outputs

 mixers 18 of the first group of P channels are supplied with harmonic oscillations

mixers 18 of the first group of P channels are supplied with harmonic oscillations

with frequencies (c + k) u) p (k 1,2, ... P) to outputs c ... from block 6. At inputs A2 ... block 6 there are no control signals, therefore the keys of 17 other channel groups the keys 16 are closed, so the harmonic oscillations at the frequency w are removed from the outputs of these channels. To measure the parameters of the signals of the second group of channels, it is necessary to send a control signal from the input A /; block 6 to the second inputs of keys 16 and 17, the third group - from the entrance A, etc.

five

The control unit 8 (FIG. 3) operates as follows.

From the output and a positive polarity pulse is fed to (t + 2) I, the inputs (R-inputs) of shift registers 19 and 20 and the inputs of gates 31 and 32, from the outputs of which a positive polarity pulse is fed to the second inputs (R-inputs RS triggers) of memory blocks 25 and 26, respectively.

Thus, the elements of block 8 are reset.

From the outputs E., .E, the phase codes and from the inputs F ... F, the address codes are supplied by a parallel-serial code to the m inputs (D-inputs) of shift registers 19 and 20, respectively, and then shifted by shift registers

19 and 20 clock pulses that arrive at the (t + 1) -th inputs of the registers 19 and 20 shift from the inputs K and

L block 8, respectively. After recording the registers of the required address codes and phase codes from the inputs M and T of the block 8, positive pulses are given to the inputs of the gates 29 and 30, respectively. From the output of the valve 29, a positive polarity pulse is applied to the second inputs of the memory unit 25 and to the input of the delay line 24, from the output of which a positive polarity pulse is supplied to the second inputs of logic elements 21, to the first inputs of which phase codes are supplied 19 shift (Q-outputs). From the output of the valve 30, a positive polarity pulse is applied to the second turns of the memory unit 26 and to the input of the delay line 23, from the output of which a positive polarity pulse is fed to the second inputs of the logic element E 22. The first inputs of which are given the address codes from the outputs register

20 shift (Q-OUTPUTS). From the output of the logic elements 21 and 26, phase codes and address codes are supplied to the first inputs (S-inputs RS-TpHrrepoB) of memory block 25 and 26, respectively. From the outputs (Q-outputs of RS flip-flops) of memory block 25, phase codes are supplied to the input mN of the corresponding keys 17, from the outputs of which the voltage levels of the required value are fed to the outputs

eleven

 Ml

G N m block

From the outputs (Q-outputs of RS-flip-flops) of memory block 26, address codes are fed to the inputs of the disinfector 28, from the N / P outputs of which levels 1 or levels

6

About are given to the outputs A ... A of block 8.

The signal extraction unit 13 (FIG. 4) works as follows.

From the input V of the block 13, the reference signal F at the frequency ujp is fed to the filter 33, the output of which is fed to the output V of the block 13. From the input X the signals

F

five

0

five

0

five

0

five

0

five

2 (k l525 ... sP) with frequencies (c + k) up are fed to the inputs of filters 34, which carry out frequency division of signals. From the outputs of the filters 24, the signals are fed to the inputs of the respective mixers 35. From the output of the generator 38, harmonic oscillation with a frequency Yp is fed to the first input of the first mixer 36 and to inputs P-2 of frequency multipliers 39, from the outputs of which harmonic oscillations with frequencies Frk (k 2 , ..., P-1) are fed to the first inputs of the mixers 36, to the second inputs of which the harmonic oscillation is applied with the frequency i) from the generator 37, the output of which is also connected to the output B of the block 13 and to the second input of the P-mixer 35, the output of which is a signal converted to frequency UJg, is applied to, output Y of block 13. From outputs P-1 of mixers 36, harmonic oscillations with frequencies i., - e (.ijp (e 1, ..., P1) are fed to outputs B ... Bj.. “BP block 13 and to the second inputs of the P-1 mixer signals to the outputs Y2 ... Y C… YP block 13.

Block 14 (Fig. 5) works as follows.

From the outputs, the Upra COMPUTER 40 issues the first address code to the outputs F, ... F | block 14, the inputs of block 41, the inputs G of the communication elements of a computer with a digital measuring device (PC computer with DSP) 42. At the same time, the inputs of block 41, computer USB with a measuring device 42 are supplied with a clock pulse IB (Input-output) from the output BB of computer 40 Under the influence of the first address code and the sync pulse IV at the output U of block 41, a positive polarity pulse appears, in addition, the CIP input (peripheral sync pulse) of the computer 40 from the output of block 41 after a time interval required to trigger the device elements negative momentum heat n The polarities, with the arrival of which - from the outputs of the EPR computer 40 are removed the second

35, from the outputs of which the frequency s. served on

the address code and sync pulse IV, under the influence of which, at the outputs L and K of block 41, clock pulses (TIs) of positive polarity appear. In addition, negative input polarity TIs start to arrive at the input of CIP computer 40 from the output of block 41 the time interval required for the device elements to operate. With the arrival of each TI of negative polarity, new address code and phase code, respectively, are supplied to the Out and Out outputs of the computer 40, respectively, as well as a clock pulse BB, and the phase codes are sent to the outputs E, .. E of block 14. After recording information in block 8 required to change the phase of the signals P of the monitored channels by i, and feed the control signal to a specific j-th input (J 1 ... N / P) of block 6 of HEADLAMP 3 (the control signal from the j-ro input of block 6 is supplied the inputs of the keys of the group of channels that are controlled) block 41 synchronization stops you Achu TI on outputs L and K, and delivers the pulses of positive polarity to the outputs T and M in addition to the input SIP computer 40 enters a pulse of negative polarity (at time interval t - dt). After a negative polarity pulse arrives at the CIP input of the computer 40, a second address code and sync pulse Bb, respectively, appear at its outputs Upr and Bb. As a result of the decoding of the new address code and the impact of the sync pulse IB, block 41 begins to output the T TI of positive polarity; With the arrival of each TI of negative polarity, a new phase code is supplied to the Vy outputs, as well as a clock pulse BB. After recording in block 8 the information necessary to change the phase of the channels monitored by 1d, block 41 stops TI at output K and supplying a positive polarity pulse to output T, In addition, a negative polarity impulse arrives at the input of the CIP 40 time interval t. - dt.). Further block 14 rag

bots in the same way. In the moment

time t, n. t (n is an even integer), the address code and sync pulse Bb appear at the outputs of the Rb and Bb outputs, respectively, as a result of which a positive polarity pulse is output from the output of the first PC computer with the D / C 42 to the output W of the block 14, which then goes to

0 second inputs P of pulse meters 15, from the outputs of which the measured values of the amplitude and phase of the signals in the binary-decimal code are fed to the inputs Z ... Zp of the PC with 1SchP 42,

5 from the outputs of which the information is alternately (from the 1st, 2nd, etc.) is fed to the inputs of the Computer 40 input, while the information from the K-th PC computer with DSC 42 (K 1,2, ...) reads after the input of the CIP of the computer 40 from the output of the K-th state of the computer - with the DSP 42 of the negative pulse, which appears at its output as a result of the input of the corresponding address code and sync pulse IB.

The operation of block 14 in the case of measuring the parameters of the signal P of monitored channels of the same group with other co-phasers is similar. The difference will be that the computer 40 controls its output immediately to the second address code. The operation of block 14 in the case of measuring the parameters of signals of another group P of monitored channels is similar.

Block 41 (Fig. 6) works as follows.

From the outputs of the PCR 40 to the inputs

0 F ... F of the decoders 43 and 44 receives the first address code, under the influence of which at the output of the decoder 43 a level 1 is set, which is fed to the first input of the logic element I 45, to the second input of which a clock pulse IB is applied. From the output of the logic element I 45, level 1 is fed to the input of the pulse generator 49, from the output of which a positive polarity pulse of the required duration and amplitude is fed to the output U of block 41, the input of the driver 51 of the pulses, the R input. RS flip-flop 54, the input of delay line 56, from which the output pulse of positive polarity is fed to the input of inverter 60, from the output of which a negative polarity pulse is fed to the input of valve 63, from which output a negative polarity output is fed to the output of CIP unit 41 Upon receipt of the second address code at the output of the decoder 44, the BaefCH level 1 is set, which is fed to the first input of the logic element 46, to the second input of which a clock pulse BB is applied. From the output of the logic element AND 46, level 1 is fed to the input of the pulse generator 50, from the output of which a positive polarity pulse is applied to the first input of the clock generator (GTI) 53, from the first output of which TI of positive polarity is fed to the output K of block 41 , the input of the delay line 55, from the output of which the TI of the positive polarity is fed to the input of the inverter 58, from the output of which the TI of the negative polarity is fed to the input of the valve

61, from the output of which the negative polarity TI is fed to the output of the CIP unit 41, the first input of the logic element 48, to the second input of which level 1 is fed from the Q output of the RS flip-flop 54, From the output of the logic element 48 of the positive polarity, 48 at the output L of block 41. After the appearance at the first exit of the GTI

53 of the required number of TIs from its second output, level 1 is fed to its second input and to the input of the pulse shaper 50. When level 1 arrives at the second input of the GTI 53, its operation stops. From the output of the pulse former 52, a positive polarity pulse is fed to the S input of the RS flip-flop 54, the second input of the logic element 47, to the first input of which a positive polarity pulse is given, whose duration is t, + ut input of the delay line 56, from the output which time interval t. - at a positive polarity pulse is fed to the input of the inverter 59, from the output of which a negative polarity pulse is fed to the input of the valve

62, from the output of which a negative polarity pulse is fed to the SIP output of the block 41, the output of the block 41. From the output of the logic element And 47, a positive polarity pulse is fed to the output T of the block 41. When the second address code arrives, the inputs

F. ... F block 41 clock pulses

-1 p

positive polarity and impulse

positive polarities are supplied only to the outputs K and M of block 41, respectively. In the future, the block 41 operates in a similar way.

Claims (1)

1. A device for measuring the amplitude and phase of the signals of a phased antenna array emitters, comprising a microwave generator connected to a probe for irradiating a phased antenna array (PAR), a multi-tap delay line whose even outputs are connected to the corresponding inputs of the first adder, and odd outputs to the corresponding the inputs of the second adder, a pulse meter, the outputs of which are connected to the corresponding inputs of the control and recording unit, the first output of which is connected to the first input of the pulse and A meter, characterized in that, in order to improve speed, a frequency conversion unit, a control unit, an inverter, an additional pulse meter signal extraction unit, the first inputs of which are connected to the first input of the main pulse meter, are input dp connecting the outputs of the respective phase shifters of the monitored HEADLIGHTS, the control inputs of the frequency conversion unit are connected to the corresponding inputs of the control unit, the reference inputs of the block and the frequency converters are connected to the corresponding outputs of the first group of outputs of the signal extracting unit, the outputs of the frequency converting unit are outputs for connecting the corresponding inputs of the accumulator of the controlled PAR, the inverter inputs are connected respectively to the even outputs of the multi-drop delay line, and their outputs respectively to the inputs of the second adder, while the outputs of the first and second adders are connected. respectively, to the inputs of the signal isolation unit, the outputs of the second group of outputs of which are connected to the second inputs of the corresponding pulse meters, the third inputs of the pulse meters are connected to the auxiliary output of the signal isolation unit, the clock outputs of the control and recording unit are connected to the corresponding inputs of the control unit whose additional outputs are outputs for connecting the corresponding inputs; their phase shifters are controlled by the HEADLIGHT, with the outputs of additional pulse measurements of the authorities. connected to the corresponding inputs of the control and registration unit. 2 "POP.1 device, characterized in that the frequency conversion unit contains N / P groups of identical channels on P channels in Each group is where N is the number of emitters in a controlled PAR, each channel consists of two keys, the first key inputs are combined and are the first channel input, the second key inputs are combined and are the second channel input, the first mixer input is connected to the first output key, the second input is the second input of the channel, and the output is connected to the output of the second key and is the output of the channel, moreover, the inputs of the frequency conversion unit are respectively the first inputs of the corresponding channel, the control inputs of the pr forming frequency are respectively connected to second inputs of the respective channels and the reference frequency converting unit inputs respectively connected to the third inputs of the corresponding channels. I 3, The device according to claims, 1 and 2, T - characterized by the fact that the block of signal allocation contains (P + 1) filter, two groups of mixers, two generators, (P-2) frequency multipliers, P filter inputs are the first the input of the signaling unit; the outputs P of the filters are connected to the first inputs of the corresponding P mixers of the first group, whose outputs are the outputs of the second group of outputs of the signal extracting unit; the output of the first generator is connected to the first input of the first mixer of the second group of mixers and to the outputs corresponding frequency multipliers, the outputs of which are connected to the first inputs of the corresponding (P-2) mixers of the second group, while the outputs (P-1) of the mixers of the second group are connected to the second inputs of the corresponding U1CICH (P-1) mixers of the first group and are corresponding the outputs of the first group of the signal extractor; the output of the second generator is connected to the second input of the Pth mixer of the first group, the second inputs (P-1) of the mixers of the second group and is the Pm output of the first group of outputs of the signal allocation unit. V (ji.2 Xjl / Yf J / / f, fmff FfT, if t L H and