SU1348806A2 - Device or pulse regulation of power in m-phase neutralless electric mains - Google Patents

Abstract

The invention relates to electrical engineering and is intended for discrete power control in electrothermal installations. The purpose of the invention is to ensure the independence of the magnitude of the impulse control period from the control resolution and improve the dynamic characteristics of the controller. In this device, regardless of the discrete control, the duration control interval is set to no more than two half-periods of the mains voltage, which ensures a reduction in the delay. 1 tabl, 4 ill. oo 00 00 about O5 N)

Description

one

The invention relates to electrical engineering, is intended for discrete control of electric power E of electrothermal installations connected to a three-phase AC network without a neutral, and is an improvement of the invention in accordance with author. No. 596930.

The aim of the invention is to ensure that the magnitude of the pulse control period is independent of the control resolution and improve the dynamic characteristics of the controller by reducing the delay.

Fig. 1 shows a functional diagram of a pulse power control device; in fig. 2 - time diagrams of the device; in fig. 3 is a functional diagram of the accumulating adder; FIG. 4 is a functional diagram of the distributor.

The pulsed power control device in the hp-phase network without neutral (Fig. 1) contains synchronizer 1 connected by its inputs to buses A, B, C of network 2, and output to the input of the first counter 3, the output of which is connected to the input of driver A , the output of the imaging unit 4 is connected to the input of the three-stroke distributor 5, the synchronous input of the trigger 6. The outputs of the distributor 5 are connected to the second inputs of the respective circuits AND 7.8, 9, the first inputs of which are connected to the corresponding outputs of the synchronizer 1, the third inputs to the pr mom trigger output 6, and outputs to the inputs of the encoder 10, whose outputs are connected to the inputs of controlled gates 11, 12, 13 connected in series with parts 14,15,16 of load to the network 2. In addition, the input of the second counter 17 is connected through the element OR 18 with the outputs of the circuits And 7,8,9, the output is connected to the input Setting zero trigger. 6. The encoder 10 contains the elements OR 19, 20, 21, the inputs of which are connected to its inputs, the inputs of elements 19 and 20 are connected to the first input, the inputs of elements 20 and 21 are connected to the first input, and the inputs 21 and 19 are connected to the third input, and their outputs are encoder outputs. Tires 22 of the adjustment interval signal are connected to a pair of. Inputs of the first accumulating adder 23, to parallel inputs of a second incandescent

but

48806

The control unit 24 is connected to the control signal terminals 25, and the OR 26 element is connected to the outputs.

Synchronizer 1 can be made in the form of an inverter, to the input of which a rectified two-half-full amplitude of up to 5 V mains voltage is applied.

10 The counters 3, 17 and the driver 4 of the control pulses can be made according to the counter circuit operating in the frequency divider mode with a variable division factor.

15 Each of accumulating adders 23 and 24 may be performed according to the scheme of FIG. 3 and includes a n-bit binary adder consisting of n one-bit binary

20 adders 27-30 and n-1-bit registers based on n-1 synchronous D-flip-flops, the first inputs of single-bit binary adders being parallel inputs of the accumulating adder, the second inputs

connected to the direct inputs of the corresponding synchronous D-flip-flops, and the outputs S of the first n-1 single-bit adders are connected to the information inputs of the corresponding D-flip-flops, whose sync inputs are connected to the clock input of the accumulating adder.

The outputs of the sum and transfer of the nth single 25-bit binary adder are parallel outputs of the accumulating adder.

The distributor 5 can be made according to the scheme of FIG. 4 based on a shift register.

A pulsed power control device in a t-phase network without neutral operates as follows. When voltage is applied to tires

45 2 network synchronizer 1 generates

sync pulses that coincide with the moments of zero transitions of the network phases, which are fed to the input of counter 3 and to the first inputs of the corresponding elements 7,8,9. Counter 3 generates synchronization pulses of the former 4 by dividing the frequency of the input sync pulses by an integer. Sync pulses arrive at

55 input driver 4, which forms a pulse power control interval, the duration of which is equal to the number of half-periods of the network voltage, which is 11

Ano in accumulator sum 2 S is written to the formers. Each control control pulse at the input of the actuator 4 commutes a single power pulse of duration T, multiple of the half-period of the mains voltage (Fig. 2) to the load-up.

The clock pulses of control are fed to the input of the distributor 5, alternating the order of connecting the circuits 7-9 to the inputs of the synchronizer 1 in time. At the same time, clock pulses are fed to the synchronization input of trigger 6, which assumes the state of its information D input, which is equal to 1 if at one of the parallel outputs that accumulate 1 of the adder 24 there is 1. At the same time, the forward trigger output signal U. everything

about

Schemes 7-9 match, remove the prohibition of their inclusion. To enable any element 7-9, a coincidence in the timing of signals 1 on all inputs is necessary. For example, if at the previous moment before the arrival of the clock pulse, element 9 was connected, after the arrival of the pulse, the distributor 5 switches to the subsequent state and connects element 7, disconnecting element 9. Subsequent clock pulse connects element 8, disconnecting element 7 (signals U, U and L respectively in Fig. 2), etc.

In either case, the output of each of the circuits 7-9, currently connected to the distributor 5, successively in time, pulses appear that are synchronous with the moments of zero crossing of the voltage of the corresponding phases of the network. So, when element 7 is turned on, pulses appear at its output, synchronous with the voltage U .., of the network, and when it is turned on, the output of the element — pulses synchronous with voltage U, at the output of the element

DC

9- pulses synchronous with voltage and. The number of pulses during the interval T between two faq control pulses is determined by the time interval during which the trigger 6 is

in state 1 and which is determined by the basis of the counting of the counter 17, equal to the number formed by the accumulating adder 24.

-

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iivjTi.cbi i.r with hihodon elements 7.8 or 9. Compressor 17 counts the number of pulses at the output of these circuits in accordance with the basis of its counting, after which at the moment of the end of the last counting pulse it gives a signal U to zero at trigger 6, locking elements 7-9 and limiting the number

10 pulses passed for

T interval in the load.

The pulses from the outputs of elements 7.8 or 9 are fed to the inputs of the encoder 10, from its outputs they are fed to the inputs 15 of controllable gates 11-13. Each pulse arrives at the inputs of two OR elements out of the three that are in the encoder, including two valves during the half-period of the mains voltage

20 three. For example, the pulses at the output of element 7, coinciding in phase with the moments of voltage crossing and zero, the network, arrive at the inputs of circuits 19 and 20, simultaneously turning on valves 11 and 12 (signals U and and, in Fig. 2) and connecting parts 14 and 15 of the load to the phases A and B of the network and during one half period of the network each. The pulses at the output of the circuit 8, syn30 chased with voltage U

The setp simultaneously arrives at the inputs of the valves 12 and 13 (signals U and and, -), connecting parts 15 and 16 of the load to phases B and C of the network, and the pulses at the output of circuit 9 are connected similarly to parts 16 and 14 of the load to phases C and A network.

Thus, the device interleaves (order) using the mains phase and power consumption from these phases in time.

35

de

RSL

lv

Another (reverse) order is possible.

connection of phases P.- lv

p p

CHAPTER 8: WHAT is achieved by change

the direction of switching of the distributor 5.

Let us now consider the method of forming the accumulating adders 23 and 24 numbers, which are the settings for the generator 4 and the counter 17, respectively, and arriving at their parallel inputs.

The idea of a method for generating settings that allows for ensuring that the magnitude of the pulse control period is independent of the control resolution and reduce latency is as follows.

At the beginning of each adjustment interval, the device receives n-bit binary codes of the control signal and M numbers equal to 1 / V, where D is the control resolution. The device according to the main auth. No. 596930 fulfills the task of passing the load of N elementary power packages (in the particular case of half-periods of the mains voltage) from M constituting the adjustment interval.

In the proposed device, instead of the numbers M and N, the settings M and N, which are the highest bits of the numbers M and N, respectively, are used for adjustment, and the device passes N half-periods into the load for the adjustment interval equal to M half-periods of the mains voltage. At this time, the residues (M-M) and (N-N 2) formed at this time are remembered and taken into account in the next adjustment interval by adding them to the numbers M and N.

The operations of allocating the higher bits and taking the younger ones into account in the next adjustment interval are carried out in accumulating accumulators.

Consider the operation of the device as a whole with a specific example (for ease of understanding in the decimal code).

Let N b, M 14. By writing down the numbers N and MB in the form 06 and 14, respectively, we single out their highest bits:

g

N

 O, M 1, which as settings arrive at the parallel inputs of the counter 17 and the driver A, respectively. The first clock pulse from the output of synchronizer 1 through counter 3 (we take its counting base equal to 1) enters the input of shaper 4, the contents of which is 1, subtracts one, and at the output of shaper 4 a signal appears that switches the valve to the next state clock inputs of accumulative adders 23 and 24. However, none of the outputs of the elements 7–9 of the signal appears, since numbers 17 and 14 + 8 are generated in the counter 17 of the record-55

san zero and, therefore, direct vyra- 22, respectively. Senior bits

the course of the trigger 6 is in zeroNO and M2 are recorded according to the state, locking the elements 7-9, respectively, in the counter 17 and forming a timed spacer 4.

, and the remnants

(N-N 2) 2 OstaTac, the first adjustment interval, equal to one half-period of the mains voltage, does not receive a power pulse to the load.

The remains of N-N 2 6 and 2 4 recorded respectively in the accumulating adders 24 and 23. The signal of the driver 4 is fed to

 the clock inputs of accumulating adders 23 and 24, when this occurs the operation of addition in accumulating adder 23 (14 -i-4 18), in accumulating adder 24 (6 6 12),

5 and the parallel inputs of the former 4 and the counter 17 receive the oldest bits K 1 and N 1 (M-M 2M 8 and, respectively, in accumulating

0 accumulators 23 and 24. A unit is recorded in counter 17. The unit from the parallel outputs of the accumulating sum-mator 24 through the circuit OR 26 is fed to the information input of the trigger

5 6.

The second clock pulse subtracts the recorded unit from the driver 4, and the signal that appears at its output goes to the distributor, redirecting it to the next state

(for example, 1 is fed to the input of element 8) and to the synchronous input of the trigger 6, tilting it to a single state. This opens element 8, a signal is sent to the control inputs of the thyristors (12 and 13), the thyristors are unlocked, and in part of the load 15 and 16 a power pulse is received. The signal from the output of the circuit 8 through the element 18 is fed to the input of the counter 17, the contents of which is equal to 1, subtracting one from it, and the signal that appears at the output of the counter 17, overturns the trigger 6

5 zero lock elements 7-9.

So, in the second interval of adjusting the duration of one half-period of the mains voltage, a power impulse enters the load, which

0 corresponds to the division ratio K 1 M.

The same signal shaper 4, arriving at the clock inputs of the accumulating adders 23 and 24, in

five

7G3

The third and fourth sync pulses at the input of driver 4 reduce its contents to zero and the signal appearing at its output switches the distributor 5 to the next state, supplying 1 to the input of element 9. But since the counter 17 records zero, the trigger 6 also The elements are in the zero state, the elements 7.8 and 9 are locked, and for the adjustment interval equal to two half-periods of the mains voltage, no power pulses enter the load, which corresponds to the division factor K 0/2.

Continuing to reason in a similar way, we will put the results in a table.

As can be seen from the table, for five adjustment intervals, the maximum of which is equal to two half-periods of the mains voltage, three half-periods of the mains voltage from seven are passed into the load, and in the accumulating adders 23 and 24 are written

zeros, i.e. the errors of the previous adjustment intervals have been fully worked out.

Continuing the table, we will see that of the next seven half-periods of network voltage, the load will pass three.

Of the 14 half-periods of the mains voltage, 6 are passed into the load, which

and corresponds to the initial task N 6; M 14; By 6/14.

We note the main feature of the scheme. Since the remainder consisting of (n-1) lower-order bits of an n-bit binary word cannot exceed 2 -1, the sum of this remainder with this binary word cannot exceed (-1) + (2 - 1) ++ 2 -2.

The allocation of bits older than degree (n-1) is equivalent to dividing a number by 2. Therefore, the higher bits n (n + O-th sums of the number with the previous remainder, which are the setpoint for the counter 17 and the former 4, cannot exceed

h + 1

 3 3.

Thus, the maximum setting is equal to the nearest smaller integer, i.e. two.

Consequently, regardless of the control resolution discretization, the driver 4 in the proposed device sets the control interval with a duration of no more than two half-periods of the mains voltage, which achieves independence of the control interval from the discreteness and improvement of the dynamic characteristics of the controller by reducing the delay.

Claims (1)

Invention Formula Pulse power control device in the t-phase network without neutral auth.St. No. 596930, due to the fact that, in order to ensure that the magnitude of the pulse control period is independent of the control resolution and improve the dynamic characteristics by reducing the delay, two accumulating adders and the OR element are introduced into it, the trigger is provided with a third input, and the first input serves as an input synchronization, second input - input Setting zero, third input - information input, the second counter is made with a control input, clock inputs of accumulating adders and a synchronization input trigger connected to the output of the pulse former, the parallel outputs of the sum and the transfer of the higher bit of the first accumulating adder are connected to the parallel inputs of the pulse former, and the second accumulating adder are connected to the parallel inputs of the second counter and the OR element with the information input of the trigger, the parallel inputs of the first accumulating adder are connected to the OR control signal buses, and the parallel inputs of the second accumulating adder are connected to the control signal buses. FI.1 Tantobian entrance Fig j Compiled by O. Parfenova Editor A. Makovska Tehred M. Khodanych Order 5189/47 Edition 862 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk on b., d. 4/5 Production and printing company, Uzhgorod, st. Design, -4 Ui.it Proofreader V. But ha ha Subscription