SU1749990A1 - Device for synchronizing converters picked up and carried common load for parallel operation - Google Patents

Abstract

The device contains a master oscillator (1), 4 controlled keys (2-5), 2 pulse sequence makers

Description

The invention relates to electrical engineering, can be used in backup power supply systems with static converters, and is intended to synchronize converters that are included in parallel operation for a common load in a system of guaranteed power supply to consumers.

A device for synchronization of a converter included in parallel operation (carrying out a method of transmitting power in synchronous mode to AC buses with electric motors connected to them), contains blocks for measuring phase difference, speed and accelerating phase difference variation and predicting zero phase difference. to determine when the converter is connected to the AC busbars with a specific lead.

A disadvantage of the known device is the complexity of its technical implementation.

A device for synchronizing converters containing blocks is known.

to determine the phase difference of the synchronized voltages and to determine (predict) the moment preceding the synphase, in fact, the tendency to a decrease in the value of the phase difference is detected.

The disadvantage of this device is the complexity of its technical implementation.

The closest in technical essence and the achieved result to the invention is a device for synchronizing converters included in parallel operation, containing for each converter a master oscillator with two synchronization inputs, a pulse distributor, the outputs of which are used as device outputs, two pulse sequence generators with a duration pulses 180 el.grad., four controllable keys, the control input of the first controllable key is connected to the output of the photo unit command for parallel operation, the control inputs of the second and third controlled keys are connected to the output (L

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the buoyk house to form a command to turn on the device in master or slave mode, the output of the first control key is connected to the first clock input of the master oscillator, the input of the first control key is used to connect to the clock output of the master device, the second control key is connected to the output of the master oscillator , the output of the second controlled key is used as the synchronization output, the input of the third controlled key and the first inputs of the two phase detectors are connected to the outputs of the dist pulse distributor through the first pulse shaper, the input of the second pulse shaper is used to connect to the network, its output is connected to the input of the frequency multiplier and the second input of the first phase detector, the second input of the second phase detector is used to connect to the output of the third controlled master key, the output of the frequency multiplier is connected to the input of the fourth controlled key, the control input of which is connected With the output of the command block for parallel operation with the network, the output is connected to the second clock input of the master oscillator, the OR element, and two phasing signal shapers.

This device synchronizes the converters by pre-synchronizing the control system of the converter connected in parallel with the master converter or with the network and switching on the power section and then switching on the switching device connecting the output circuits of the converter to the busbars or buses of the network. However, it does not provide the possibility of switching on parallel operation of converters operating in the power mode of consumers.

The aim of the invention is to enhance the functionality of the synchronization device and increase the reliability of the power supply to the consumers by ensuring that the converters operating in the power supply mode are switched on in parallel.

To do this, a D-trigger is introduced into the proposed device. the counter and the element AND- NOT; These elements are connected so that the output of each of both phase detectors through the corresponding shaper of the phasing signal and the OR element is connected to the D-trigger trigger input, the output of the master oscillator is connected to one

the input of the NAND element and the counting input of the counter, the R input of which is connected to the inverse output of the D-flip-flop and another input of the NAND element, the output of the counter corresponding to the Q 21. is connected to the R-input of the D-flip-flop, D - whose input is used to supply a logical unit, and the input of the pulse distributor is connected to the output of the NAND element,

0 The introduction of additional elements allows the device to provide synchronization of converters operating in the power mode of consumers. Consequently, the proposed device is given5 wider functional capabilities and the reliability of the power supply to consumers beyond the exclusion of the power interruption, which is possible during the preliminary synchronization by the prototype device, is increased.

The drawing shows a structural diagram of the proposed device.

Device for synchronizing converters included in parallel

5 operation for a common load, for each converter contains a master oscillator 1 with two synchronization inputs, four controllable switches 2-5, a pulse distributor 6, generation units

0 commands for parallel operation 7, 8 and for switching on the master or slave 9, phase detectors 10 and 11, phasing signal drivers 12 and 13, OR 14 element, pulse drivers after 5, 15, 16, frequency multiplier 17, clock driver 18 The control input of the first control key 2 is connected to the output of block 7, the control inputs of keys 3 and 4 are connected to the output of block 9, the output of the first key 2 is connected to the first clock input of master oscillator 1, the input of key 2 is used to connect to the sync output tion master device, the second switch 3 is connected

A 5 input with an output of the master oscillator, the output of the second key 3 is used as the synchronization output, the input of the third key 4 and the first inputs of the phase detectors 10 and 11 are connected to the outputs of the pulse body through the pulse sequence shaper 16. The input of the pulse shaper 15 is used to connect to network. Its output is connected to the input of the multiplier 5 of frequency bodies 17 and the second input of the phase detector 10. The second input of the phase detector 11 is used to connect to the output of the control key 4 of the master device. The output of the frequency multiplier 17 through the driver 18 is connected to the input

control key 5, the control input of which is connected to the output of the command block 8 for parallel operation with the network. The output of the key 5 is connected to the second synchronization input of the master oscillator 1. The device also contains an additionally introduced group of elements 19 consisting of a D-flip-flop 20, a counter 21 and an IS-NOT element 22. The sync-input of the D-flip-flop 20 through the OR 14 element and drivers 12 and 13 are connected respectively to the outputs of the phase detectors 10 and 11. The output of the master oscillator 1 is connected to one input of the NAND element 22 and the counting input of the counter 21, the R input of which is connected to the inverse output of the D flip-flop 20 and another input of the AND element NOT 22. Counter output, according to favoring discharge dy Q 21 is connected to the R-input of D-flip-flop 20, D-input of which is used to supply a logic one and the output pulses of the distributor 6 is connected to the output of AND-NO element 22.

The device works as follows.

When the converter is turned on for parallel operation with the master, the pulses of the master oscillator, which is switched on in master mode via key 3, act on the first synchronization input of the slave via key 2, as a result of which the slave master oscillator operates synchronously with the master. However, due to the ambiguity of the initial states of the pulse distributors, the control pulses for the valves and, accordingly, the output voltages of the converters can be out of phase. To implement phasing of output voltages of converters switched on for parallel operation when powering consumers, for example, when connecting a converter from standby mode to a working converter or to a network, additional elements (group 19) are introduced into the synchronization device, providing phasing by outputting once in each period time of the converter doubles the period of the pulses of the master oscillator arriving at the distributor 6. For this, the generated driver 12 or 13 pulse signals phasing trigger switch 20, establishing on its inverted output logic level zero, allowing the counts of the counters 21 which akaichivaets when the trigger 20 returns to the initial state when a difference occurs per unit of zero at the counter output. Inverse trigger output 20 in this case prohibits

during the existence of a zero level on it, the passage of 22 pulses of the master oscillator to the distributor I-NE, since the pulsed 5 phasing signal is generated once during the period of the output voltage of the converter, respectively, the period of the pulses of the master oscillator increases once,

Claims (1)

0 arriving at the distributor. This change in the pulse period provides for the phasing of the control pulses of the converter with similar pulses of the master converter or with the network voltage, and hence the output voltage of the converter. In this case, the phasing process occurs without unacceptable phase jumps and ends in a time not exceeding the number of periods equal to the division ratio of the pulse distributor. Apparatus of the Invention A device for synchronizing converters included in parallel 5 work on a common load, containing, for each converter, a master oscillator with two clock inputs, a pulse distributor whose outputs are used as device outputs, two pulse sequence makers with a pulse duration of 180 hl.d., four controllable keys, a control input The first controlled key is connected to the output of the block. 5 commands for parallel operation — the control inputs of the second and third controlled keys are connected to the output of the command generation unit for switching the device into master or slave mode, 0 the output of the first control key is connected to the first synchronization input of the master oscillator, the input of the first control key is used to connect to the synchronization output of the master device, the input of the second control key is connected to the output of the master oscillator, the output of the second control key is used as the synchronization output , the input of the third controllable key and 0 the first inputs of two phase detectors are connected to the outputs of the pulse distributor via the first pulse shaper, the input of the second pulse shaper is used to connect to the network, its output is connected to the input of the frequency multiplier and the second input of the first phase detector, the second input of the second phase detector is used for connection to the output of the third controlled the master key, the output of the frequency multipliers is connected to the input of the fourth controlled key, the control input of which is connected to the output of the command block for parallel operation with the network, the output is connected to the second synchronization input of the master oscillator, the OR element and two phasing generator signal, due to the fact that, in order to expand functionality and increase reliability, it is equipped with a D-trigger, a counter, and an AND-NOT element, with the outputs of both phase detectors 0 through the corresponding phasing signal shaper and the OR element is connected to the synchronization input of the D-flip-flop, the output of the master oscillator is connected to one input of the NAND element and the counting input of the counter, whose R-input is connected to the inverse output of the D-flip-flop and another input of the NAND element , the output of the counter is the corresponding bit Q and: 21 is connected to the R-input of the D-flip-flop, the D-input of which is used to supply a logical unit, and the input of the pulse distributor is connected to the output of the NAND element. On on couple l work with se / i drink Inkhroiml leading zg 2nd hod sync Zkl zg In the mode of the eight and slave Sinhroiml dm poor To the phases of the detector IT8boMttfX