SU1109739A1 - Device for ranking numbers - Google Patents

Abstract

A DEVICE FOR RANKING NUMBERS containing (, M-1 | yy-bit shift registers, where N is the number of sorted numbers, (N-ncircuits for comparing two tp digit numbers and the unit for counting the number of the input number, and the output i-ro t -shift shift register, where, 2 (N-1), is connected to the first input of the i-th comparison circuit, output j-ro of the m-bit shift register. where j 1,2, ... Dm -2) , is connected to the input j + l of the t-bit shift register, the second inputs of all comparison circuits are connected to the input numbers bus and the input of the first m-bit shift register, and the outputs to the inputs of the block In calculating the number of the input number, the device shift bus is connected to the clock inputs of all m-bit shift registers, characterized in that, in order to reduce hardware costs at large N values, the device contains | -shift shift registers, where g is the number of rank bits and IN is lJ KOppeKTopoB of rank, the equalizer contains two comparison circuits and b is a bit adder, with the outputs of the count block of the input number rank connected to the inputs of the first n-bit the shift register, the outputs of which are connected to the corresponding inputs of the first group of the adder of the first rank corrector and the corresponding inputs of the first groups of the first comparison circuits of all the correctors of the rank, the inputs of the second groups of the comparison schemes of the first corrector of the rank and the inputs of the first groups of the second Comparison schemes for all rank adjusters are connected to the corresponding N-ro outputs of the n-bit shift register, the h-bit totalizer outputs of the i-th equalizer rank adjuster. are connected to the corresponding inputs (+1) of the G-bit shift register and the outputs of the i-ro rank of the device number, the outputs of the h-bit shift register, where, 3 ,. .., (m-1), connected to the inputs of the first group; About a P-bit adder and inputs of the second group of comparison circuits It-th 00 corrector rank, in each rank corrector the output of the first comparison circuit is connected by q transfer input of the summator The output of the second comparison circuit is connected to the combined inputs of the n-bit sum-ror, the synchronizing inputs of all n-bit shift registers are connected to the device shift bus, the outputs of the rft-bit shift registers are outputs of the device numbers to be ranked.

Description

1 The invention relates to computing and can be used in specialized computing machines and data processing devices. A device for ranking numbers is known, containing a shift register for storing numbers, a buffer register of a reference number, a comparison circuit of a rank number calculating device, AND, OR elements, a control unit, a synchronization unit, a comparison cycle counter, a counting number counter, a cycle end determining unit, This unit is used to determine the rank of the number taken as the reference from a sequence of numbers after a cycle. To determine the ranks of all sequence numbers in this device, N tact is required. The closest to the proposed technical entity is a device that has a higher speed and solves the problem of determining all sequence numbers (n-1 | shift registers) for one tick of ranks. -bit numbers, (NI) circuits of two m-digit numbers, N blocks counting the number of ranksN -3Nt of one-bit registers and - are NOT elements, output i-ro shift register, where i 2,3,., { N-1) connected to the first input -and Hema comparison, comparison circuits second inputs connected to a bus input of numbers and c. the input of the first shift register, the input of the i-ro shift register is connected to the output (il) -ro of the shift register, the output of the j-th comparison circuit, where j 1,2, ..., {NI), is connected to the input of the first one-bit register from a chain of serially connected (N - 1-j) odnoprazp bottom registers, to one of the inputs of the first rank counting unit and through the corresponding element NOT to one of the inputs (j +)) - ro rank counting unit, output of the kth single bit register in the j-th chain of one-bit registers, where to 1, 2, ... , (N -1 - j), connected to one of the inputs 1k + 1) of the rank number counting unit and through the corresponding element NOT to one of the inputs (k + rank number counting unit, the synchronization inputs 9 of all registers are connected to the bus device shift signals, a rank number counting unit contains an adder c (Nl) inputs connected to the rank number counting unit inputs, and the output of the adder is connected to the output of the rank number counting unit 2J. A disadvantage of the known device is a complication of the device with an increase in the number of sorted numbers. invented nor is the reduction of hardware costs for large values of N. The goal is achieved by the fact that in a device for ranking numbers containing (N-1) t - bit shift registers, - where N is the number of sorted numbers, (N-ljcxeM compare two-pn-bit numbers and a block for counting the number of the input number, where the output of the i-ro m-bit shift register, where il, 2 ,, ..., (N-1), is connected to the first input) of the comparison circuit, output of the jth t-bit. shift register where ,. , 2, ... , (N-2), is connected to the input of the (j + l) th m-bit shift register, the second inputs of all comparison circuits are connected to the input numbers bus and the inputs of the first fn-bit shift register, and the outputs to the inputs of the block counting the number of the input number, the device shift bus is connected to the synchronization inputs of all m-bit shift registers, it contains N fi-bit shift registers, where n is the number of rank bits, and (N -1) rank correctors, rank corrector contains two comparison circuits and an n-bit adder, with the outputs of the rank number counting block one number is connected to the inputs of the first p-bit shift register, the outputs of which are connected to the corresponding inputs of the first group of the adder of the first rank corrector and the corresponding inputs of the first groups of the first comparison circuits of all the correctors of the rank, the inputs of the second rjjynn comparison schemes of the first corrector of the rank and the inputs of the first groups of the second Comparison circuits for all rank correctors are connected to the corresponding outputs of the Nth n-bit shift register, the outputs of the n-bit totalizer of the i-th rank equalizer are connected to the corresponding input. om (i + l) -ro n-bit shift register and outputs of rank i-ro device number, outputs of the n-th n-bit shift register, where, 3 ,, .., (M-), are connected to the inputs The first group of n-bit adder and the inputs of the second group of comparison schemes of the rank corrector, in each rank corrector, the output of the first comparison circuit is connected to the transfer input of the adder, the output of the second comparison circuit is connected to the combined inputs of the h-discharge totalizer, the synchronization inputs of all n-bit single shift registers are connected to the device shift bus; m-bit outputs are The shift bars are the outputs of the device's ranked numbers. Figure 1 shows a block diagram of a device for ranking numbers; in fig. 2 - rank corrector structural diagram; in fig. 3 and 4 - correction process for the case. The device contains an input bus 1 through which a sequence of numbers expressed by an m-bit parallel code is supplied, an m-bit shift register 2 (the total number of registers is N), a circuit 3 comparing two .t-bit numbers, a block 4 rank number counts 4 {input adder), n-shift shift register 5, delaying information by one clock (total number of registers is N + 1), rank corrector 6, bus 7, outputs 8 ranked numbers, outputs 9 corresponding input numbers, bus 10, through which the value of the current is applied to the corrector angaR, expressed by the h-bit parallel code, input buses 11–13, which receive values of the current rank R, rank R, worked with the sl-slider adder 4 and passing the first register 5 shift of the chain of registers (Fig. 2), and rank Rg out of the last register of 5 shift of the chain of registers, circuits 14 and 15 comparing two n-bit numbers. The voltage at the output of the comparison circuit is equal to the logical unit HYiC irr where UdI Us - respectively, the numbers at the inputs of the L and B circuits compared to. The device also contains a P-bit parallel adder 1 and an output bus 17. The device operates as follows. On the input bus 1 (Fig. 2), each clock cycle receives a number, expressed in a t-bit parallel code. Through N clocks from the outputs of series-connected m-bit registers 2, the inputs to input 1 in N consecutive clocks are fed to the inputs of the comparison circuits 3. The numbers in the comparison circuits 3 are compared with the input number that came on the input bus 1 of the B (N + I) -M cycle. If the input number B (N + nM cycle is equal to or greater than the number taken from the output of one of the registers 2, the output of the corresponding comparison circuit 3 produces a signal equal to the logical one. If the number on the input bus 1 is less than the number from the output of the register 2, the output of the corresponding comparison circuit 3 produces a signal equal to logical zero. The signals from the outputs of the comparison circuits are fed to the N-input adder 4 (unit counting circuit J.) The output of the adder produces a number Pgj expressed by parallel n-bit binary code when The number of Rgjj characterizes the number of the rank of the (N + 1) -th number of the input sequence in a given clock cycle. Obviously, depending on the result of the comparison, the (N + 1) -th input number with N numbers at the outputs of the registers 2 Rgy can take any value within O ... N. The value of the number paHraRgj (N + l) -th number of the input sequence produced in the N input adder 4 is input to the chain from the series-connected shift registers 5. The current values of the rank number R are shifted along the chain of shift registers 5 in the same way as the values of the input numbers move along the chain of shift registers 2. Each of the N numbers of the input sequence, located at the outputs 8 of the chain of registers 2, corresponds to the rank of this number at the corresponding output 9 of the chain of registers 5. However, the rank Rg defined for the (N +1) -th number of the input sequence does not necessarily remain unchanged for the whole time the number is in the ranking window: in N ticks, the contents of the ranking window changes completely and, consequently, the rank of the same number can vary from one measure to another. To obtain the true current values of paijra N input numbers in series with the 5 shift registers. Rank correctors 6 are included. Their purpose is to correct the current value of rank R depending on the ranks of the numbers entering and leaving the ranking window. The correction process for the particular case is schematically illustrated by fig. 3 and 4. NUMBERS along the horizontal axis denote the numbers of the ranks of the numbers contained in registers 5, and the same rank K coming to the first equalizer 6 from the first shift register 5, and the rank B coming out of the last shift register 5. FIG. Figure 3 shows the case of bx out. In this case, the assigned rank of the input number in the previous cycle, Rc without change (without correction), remains the rank of this number; within R g L1x i 6x, current ranks in are down by one. FIG. 4 shows the case of R R. In this case, the rank developed in the previous tact and all current ranks within Rgx R are increased by one. As a result of the correction in accordance with the stated logic, the output codes 9 of the correction circuits form the current rank codes N numbers of the input sequence, having values from 1 to N, if there are two or more identical numbers in the ranking window with the number received later. The specified logic is implemented in the rank offset circuit (Fig. 2 All N rank offsets, included in the device, are made in the same type pattern. Differences in the switching circuit of the first corrector compared to the basic ones are shown in Fig. 2. The corrector contains two comparison circuits h -digit numbers (14 and 15), generating a logical unit signal (V and Vg are the numbers at the inputs / and in the Equation and -digit parallel accumulator 16. The number that goes to the inputs A -A | of the first term of the adder correction. The output of the comparison circuit 14 is connected to parallel the included inputs of the second adder adder, the output of the comparison circuit I5 is connected to the transfer input of the adder. If there is a logical unit at the output of the comparison circuit I5, the number applied to the inputs, but increased by one, is removed from the output of the adder. the numbers supplied to the inputs of the adder are increased by 1 + 2 + ...., which for a .h-digit is equivalent to decreasing its value by one. If the outputs of the circuits 14 and 15 are simultaneously zeros or ones, the value of the signal .5 -5 at the outputs. JiyMMaTOpa coincides with the value of the number applied to the inputs A. -A „of the adder. In the first equalizer installed at the beginning of the chain of registers 2, the comparison circuit 14 always receives the inputs / 4 and B in the same number and produces a logical zero signal. In the comparison scheme I5, the ranks Rg and Rg are compared and the signal of the logical unit is generated at the RC. In this case the rank of the input number is increased by one. In the other offsets, the comparison circuit 14 generates a signal of the logical unit when., J, the comparison circuit 15 - when, - Rg. Thus, the value of the current rank Rf remains unchanged when "BXJ b-Raxj is increased by one while." L1 (". g which corresponds to the principles of rank correction set forth above. Feasibility studies, we will make a comparative assessment of the complexity of the construction of the proposed device in comparison with the known (basic device J. Assessment will be made by the number of elements. Total The number of elements in the proposed device is equal to + K, ,,:, where ((. - the number of rvi is the resolution of the respiratory shift registers 2 () is a number of comparisons,), K is the number of N-input adders (. C number, p-bit shift registers (K is the number of one-bit registers N 2 3 4 5 6 7 8 9 M 5 11 19 29 41: i55 71 89., K 18 20 36 46 56 68 74 87

From the table it follows that the expediency in the application of the proposed device occurs when. In particular, in one of the options for building hardware, it became necessary to develop a device for ranking 16 numbers.

The use of the proposed construction made it possible to almost halve the number of elements of the device. As a result, the volume of the device was reduced by half, the process of setting up and testing the device was simplified, since the proposed device 1109739 5 O zl: in

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consists of one-type, repeating elements.

If the cost of the components used to manufacture the known device at 14 16 on the basis of the use of 133 series microcircuits is 1350 rubles, then the cost of the combined products in the proposed device when using the same 133 series microcircuits is 830 rubles, i.e. there is only a saving on components x 520 rubles. .8 shifts of the Kj N + 1, (N + -t | where 3 X U is the smallest integer, not the number of cvm 14 comparison (or L5)); K / - the number of p-razdnk Parallel adders: the estimate of the number of enp-s in the scheme of the known (M) and Supplied Device (K) is equivalent to the table. , 10 15 16 109 239 271 98 154 166

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Claims (1)

DEVICE FOR RANKING NUMBERS containing (1H-1) t-bit shift registers, where N is the number of sortable numbers, (N-11 schemes for comparing two m-bit numbers and a block for calculating the rank number of the input number, and the output of the i-th bit shift register, where i = 1, 2, ..., (N-1), is connected to the first input of the i-th comparison circuit, the output of the j-th h-bit shift register. where j = l, 2, .. ., (N-2), connected to the input of the (j + 1) th h-bit shift register, the second inputs of all comparison circuits are connected to the input number bus and the input of the first h-bit shift register, and the outputs to the inputs of lok of counting the rank number of the input number, the device shift bus is connected to the synchronizing inputs of all m-bit shift registers, characterized in that, in order to reduce hardware costs at large values of N, the device contains N l-bit shift registers, r, η - the number of bits of the rank, and (Ν - 1 £ rank corrector, the corrector J> aHra contains two comparison schemes and a d-bit adder, and the outputs of the unit for calculating the rank number of the input number are connected to the inputs of the first η-bit shift register, the outputs of which are sub are connected to the corresponding inputs of the first group of the adder of the first rank corrector and the corresponding inputs of the first groups of the first comparison schemes of all rank corrector, the inputs of the second groups of the comparison schemes of the first rank corrector and the inputs of the first groups of the second comparison schemes of all rank corrector are connected to the corresponding outputs of the nth the shift register, the outputs of the h-bit adder i -ro of the rank corrector under · ?, are connected to the corresponding inputs (i + l) -ro of the η-bit shift register and the outputs of rank t-ro of the device number, the outputs are k ^_ ro h-bit nuclear shift register, where k = 2,3 ,. .., (No. I), connected to the inputs of the first group of the d-bit adder and the inputs of the second groups of comparison schemes of the k-th rank corrector, in each rank corrector the output of the first comparison circuit is connected to the transfer input of the adder mat, the output of the second comparison circuit connected to the combined inputs of the η-bit adder, the clock inputs of all η-bit shift registers are connected to the device shift bus, the outputs of the h-bit shift registers are outputs of the device’s ranked numbers. 1 ’1109739