SU1346948A1 - Device for checking operation of automatic frequency control of phase circuit operation - Google Patents

Abstract

The invention relates to radio engineering and automation and can be used to monitor the functioning of phase locked loop systems. The purpose of the invention is to expand the functionality of the device. For this purpose, an element 9, a pulse shaper 10 and shift registers 7 and 8 are introduced into the device. The device also contains the element AND-NOT 1, phase detector 2, resistors 3 and light-emitting diodes 4, forming the indicators 5 and 6 of reference. When one of the input signals to the first input of the phase detector 2 disappears, a low voltage level is established at its output for the entire time of the absence of a signal, and all the light emitting diodes of the second indicator are illuminated. When the signal arriving at the second input of the phase detector disappears, a low level is established at its first output, and the light output is light. reading diodes of the first indicator of reference. 1 il. п с (Л 00 4; о со 4 00

Description

The invention relates to radio engineering and automation and can be used to monitor the functioning of phase-locked loop systems. you (pLL).

The purpose of the invention is to expand the functionality of the device.

The drawing shows a block diagram of the device.

The device contains the element AND NOT 1, the first and second inputs of which are connected respectively to inverse

the outputs of the phase detector 2, the post-15 state of the second register 8 of the shift coherently connected resistors 3 and light-emitting diodes 4, forming the first 5 and second 6 reference indicators |, the outputs of each stage of the first 7

does not change.

At the end of the negative pulse, the auxiliary frequency pulses are applied to the clock inputs.

 and-second 8 shift registers junction-jO of the first 7 and second 8 shift registers

with the corresponding inputs of the first 5 and second 6 indicators of reference, the information inputs of the first 7 and second 8 shift registers are connected respectively to the first and second inputs of the AND-NE element 1, the output of which is connected to the first input of the AND 9 element and through the pulse shaper 10 - with the installation inputs of the first 7 and second 8 shift registers are clock inputs of which are connected to the output of the element 9, the second input of which receives the auxiliary frequency signal.

The device works as follows.

In accordance with the principle of the phase detector in the PLL circuit synchronization mode, the first or second inverse outputs of the phase detector 2, depending on the phase shift 5, negative pulses appear. At the output of the element NAND 1 there will be positive pulses, on the rising front of which in the pulse shaper 10 short pulses are formed.

Under the action of these pulses, the first 7 and second 8 shift registers are set to one. If negative pulses appear at the first output of the phase detector 2, during the duration of each negative pulse through the AND 9 element, the clock inputs of the first 7 and second 8 shift registers receive impulses of the auxiliary frequency, the source (not shown; which may be a separate quartz crystal).

a generator or a crystal oscillator used in the PLL circuit to form a reference signal, followed by dividing (if necessary) their frequency to the desired values. Under the influence of these pulses, the logo O is recorded in the cascades of the first shift register 7, since at its information input there is a Log level. A. In the cascades of the second shift register 8, a log is written, 1, since there is a log level on its information input. 1, t, e.

the state of the second register 8 shift

does not change.

At the end of the negative pulse, the auxiliary frequency pulses are applied to the clock inputs.

ha ceases.

The light-emitting diodes 4 of the first indicator of 5 readings are connected to the cascades of the first shift register 7, in which the Log is recorded. Oh, the light of the vehicle, the remaining light-emitting diodes 4 of the first indicator 5 count, and all the light-emitting diodes 4 of the second in

Dicator 6 countdown redeemed.

When the next negative pulse appears at the first output of the phase detector 2, the described process repeats. Since the pulses at the first output of the phase detector 2 follow with a sufficiently high frequency, it seems that the light-emitting diodes of the first indicator 5 of the reference light are continuous, forming a luminous column.

The number of light cix of light-emitting diodes 4 of the first indicator 5 of reference depends on the magnitude of the phase shift in the PLL circuit, i.e. with an increase in the phase shift, the number of luminous light-emitting diodes 4 of the first indicator 5 of reference increases, and the length of the light column increases accordingly.

The number of cascades of the first 7 and second 8 reg: isters of the shift is determined by the following relation;

3601 p

Ji

where l If is the price divided by the phase of the reference indicator. In this case, the auxiliary frequency f, should be

-8Cn

 n. f

on

where f,

on

the reference frequency supplied to one of the inputs of the phage detector 2.

When negative pulses appear at the second output of the phase detector 2, in accordance with the change in the sign of the phase shift in the PLL circuit to the opposite, all processes in the proposed device; pass in the same way as described, but in this case only the corresponding light-emitting diodes A of the second indicator 6 are counting.

In the absence of synchronism in the PLL circuit, the duration of negative pulses, for example, at the first output of the phase detector 2, changes with a difference frequency from the minilink value to the maximum, b as a result of this, all light-emitting diodes 4 are illuminated on the first indicator 5 of the reference signaling the presence of synchronization failure PLL circuit.

If the synchronization failure in the PLL circuit occurred at the sign of the phase shift opposite to the previous one, then in this case the light of the Tc is all light-emitting diodes 4 of the second indicator 6 of the reference.

When one of the input signals arriving at the inputs of phase detector 2, for example, at the first input, disappears, its second output sets a low level to everything. no-signal time, and all the light-emitting diodes of the second reference indicator 6 are light.

Editor N. Dumbass

Compiled by L. Sorokina

Tehred M. Khodanich Proofreader A. Zimokosov

Order 5112/40 Circulation 693

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

When the signal arriving at the second input of the phase detector 2 disappears, a low level is established at its first output, and all the wave-emitting diodes 4 of the first indicator 5 are illuminated.

Claims (1)

Invention Formula A device controlling the operation of a phase-locked loop, containing an NAND element, the first and second inputs of which are device inputs, a series-connected resistor and a light emitting diode, which form the first and second reference indicators, in order to extend the functionality element I, pulse generator, the first and second shift registers, the outputs of each cascade of which are connected to the corresponding inputs of the first and second reference indicators, information e inputs of the first and second indicators of the rest; information inputs of the first and second shift registers are connected respectively to the first and second inputs of the NAND element, the output of which is connected to the first input of the AND element and through the pulse shaper - to the installation inputs of the first and second shift registers, clock the inputs of which are connected to the output of the element I, whose second input is the input of the auxiliary frequency signal. Subscription