SU1345150A1 - Amplitude-time quantizer with regulated threshold - Google Patents

Abstract

1. Amplitude-time quantizer with an adjustable threshold, containing a reversible counter, a synchronizer, a memory unit and serially connected code-voltage converter, a comparator and a time discretization, the memory unit contains N shift registers, whose inputs are connected to the outputs of the same name bits The outputs of the reversible counter, and the outputs - with the installation inputs of the same-named bits of the reversible counter, the tap of each of the N shift registers is connected to the input of the code-nap converter of the same name from the N bits The first and second outputs of the synchronizer are connected respectively to interconnected clock inputs of a time sampler and N memory register shift registers and a clock input of a reversible counter, characterized in that, in order to increase the speed of threshold control in the presence of azimuthally non-stationary interference without suppressing the signals of point targets, the first and second elements of the NAND, the first and second drives, the first and second decoders, and OR elements are introduced, with the direct output of the temporary dis- the rectifier is connected via the first element IS-NOT to the summing input of the reversible counter, and through the first drive and the first decoder connected in series to the first input of the element OR, the inverse output of the time sampler is connected through the second element IS-NOT to the subtracting input of the reversible counter, and sequentially connected to the second drive and the second decoder - with the second input of the element OR, the second inputs of the first and second elements AND-NOT connected to the first output of the synchronizer, the third output of which connected to the third input of the OR gate, its output connected to the third input of the first and second AND-NO elements, and first and second outputs of the synchroniser connected respectively to the first and second clock inputs of both drives. 2. The quantizer according to claim 1, characterized in that the accumulator contains an inverter and a series-connected AND-NOT element, a counter and a multi-channel shift register, the output of which is connected to the counter enable input and is the output of the accumulator, the input and the first and second clock inputs which, respectively, are the interconnected input of the inverter and the first input of the NAND element, interconnected second input of the NAND element, and the input input of the multi-channel shift register and the clock input of the counter, and the output of the inverter union of a second input of the counter. Ш (Л. Со 4 СЛ СЛ О

Description

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The invention relates to radio engineering and can be used in signal detectors against the background of non-stationary in azimuth interference.

The purpose of the invention is to increase the speed of threshold control in the presence of azimuthally unsteady interference without suppressing the signals of point targets,

FIG. 1 shows the structural electrical circuit of the proposed quantizer; FIG. 2 is a structural electrical storage circuit; FIG. 3 shows timing diagrams explaining the operation of the proposed quantizer.

The amplitude-time quantizer with an adjustable threshold contains a comparator 15, time sampler 2, reversible counter 3, element OR 4, code-voltage converter 5, synchronizer 6, first and second elements AND-HE 7 and 8, first and second drives 9 and 10 , the first and second decoders 11 and 12 and block

13 RAMs, containing N registers

14th mi shift. The first and second drives 9 and 10 contain, counter 15, inverter 16, the element AND NOT 17 and the multichannel shift register 18.

Amplitude-time quantizer with adjustable threshold works as follows.

In each period of the following probe pulses (Fig. 3a), the first and second outputs of the synchronizer 6 generate bursts of phase-shifted clock pulses (Fig. 3 b and

at). The number of pulses in the packet and in

The interval between them, equal to the sampling step, determines the working area of the distance of the proposed device.

In each sampling element, from the output of the memory block 13, the code corresponding to the threshold level developed for this sampling element over all previous repetition periods (Fig. 3) is supplied to the input of the converter 5 by the code-voltage in the parallel binary code.

During the bin, the realization of the input process (Fig. 3c) is compared in the comparator 1 with a threshold voltage (dashed in Fig. Fig. Back) formed by code-voltage converter 5. When the signal exceeds a threshold voltage

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five

five

0

0

five

0

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(threshold) in samples 1,2, i + 1, a pulse of standard amplitude appears at the output of comparator 1 (Fig. Ze). Otherwise, the log level is generated. 0

In the time sampler 2, the quantizer output pulses are tied to the nearest clock pulses (Fig, 3b) 5 by acquiring a delay of 1} sampling unit. As a result, on the direct (FIG. 3) and inverse (FIG. 3) outputs of the sampler 2, the pulse duration is equal to or a multiple of the sampling period; The pulses from the direct and inverse outputs of the time sampler 2 through the first and second elements AND-HE 7 and 8, respectively, arrive at the summing and subtracting inputs of the reversing counter 3 (FIGS. 3 and k).

The first and second elements AND-NOT 7 and 8 are controlled by the third inputs by the signals from the output of the element OR 4, and by their inputs by the pulses (Fig. 3.b) from the first output of the synchronizer 6. In the element OR 4, the signals from the output of the first and in the second of the decoders 11 and 12 (Fig. 3 l) and the signals from the third output of the synchronizer 6,

The first second accumulators 9 and 10 in each element of the discretization accumulate, respectively, the facts of successive exceptions or non-exceptions of the quantization threshold in successive periods. The signals at the outputs of the first and second decoders 11 and 12 appear when the specified criteria are met during the accumulation process (for example, five exceedances or non-exceedances).

The signals at the third output of the synchronizer 6 are generated in each Kth following period (Fig. 3A) with a duration of no less than the processing zone and the discretization elements: The numerical value of K is chosen so that during the time the signal exits from the dotted angle of the target, one resolution pulse arrives range (for this number K must be matched with the number of pulses in the echo sheaf). In this case, independent sampling of the input process is involved in the formation of the threshold voltage.

At the beginning of each sampling element, the installation inputs of the reversible counter 3 from the memory block 13 in the parallel binary code are supplied with the number g (Fig. 3m) developed for all previous periods following this sampling element.

The zero level of the pulse of the clock sequence (Fig. Sv) from the second output of the synchronizer 6 is entered in the parallel code into the reversible counter 3 (the number 3 and),

By the positive differences at the counting inputs of the counter (Fig. 3 and K), the number in the reversible counter 3 increases or decreases by one, depending on whether the signal exceeds the threshold voltage (increments 1.2, i + 1) or does not exceed. By. The positive differential pulse (Fig. 3B) from the first output of the synchronizer 6 updated in the reversible counter 3, the number Q is entered into the memory block 13.

In those discretization elements where there is no resolution pulse, when a disturbance appears in one of the discretization elements, the first accumulator 9 in discretization elements 1 and 2 (Fig. Aft) begins to accumulate a series of units corresponding to exceeding the threshold threshold noise wives When executed in the first decoder

1Q 11 of a predetermined detection logic (for example, a sequence of 5 units) at its output and, respectively, at the inputs of the first and second elements NAND 7 and 8, a discontinuity signal is produced (FIG. 3L), which allows updating of numbers in a reversible counter 3 each follow period. In this case, the maximum increase in the rate of increase in the threshold for example 2Q marriage (in this example, 6 times) before reaching the steady state.

when P 0.5 and both accumulators 9 and 10 do not provide permission signals. At the end of the azimuth

35

the element 4 that is firing from the output (the interference voltage threshold voltage is excessive for noise (the discretization elements are L; i + 2; n in Fig. 3b); therefore, the second accumulator 10 accumulates a series corresponding to the sequence m threshold, and at its output after five periods of following less than the width of the antenna pattern, a signal is produced allowing the accelerated decrease in the code of numbers in the reversible counter 3 in each follow-up period (Fig. 3). - horn The minimum voltage is minimal while providing conditions for detecting weak targets located directly beyond the azimuthal disturbance boundary.

If the threshold of operation of the first accumulator 9 is chosen so that it is not reached when receiving a signal from a point target in the discretization element (i + 1), then the first and second accumulators 9 and 10 have no effect when receiving signals from such targets.

The correct functioning of the proposed device is provided by the temporary combination of all processes. The number of cells N in registers 14 of the shift must be matched with the number of pulses on the first and second

An example, in the element i + 2), the update of the number in the reversible counter 3 does not occur and the same number g (i + 1) that was previously read from it is written to the memory blocks.

During that period when the third output of the synchronizer 6 generates a resolution signal (for example, in every sixth following period), the numbers in the reversible counter 3 are updated in all the sampling elements regardless of the output signals of the first and second decoders 11 and 12. If on the signal input of the comparator 1 is a stationary in time noise process, and the amplitudes of the bursts in the adjacent follow periods are uncorrelated, then the output of the device is stabilized with a probability of exceeding n orog Pjjj 0.5, i.e. The probabilities of the transducer and the continuous video noise threshold voltage are equal.

In this case, the occurrence at the output of a comparator 1 series of consecutive exceedances or failures is an unbelievable event, so the first and second drives 9 and 10 under these conditions do not affect the operation of the device, and the updating of the threshold voltage (as, and the numbers in the reversible counter 3) occur in one of the six following periods.

40

45

50

55

the outputs (Fig. 3.6, c) of the synchronizer 6, so that before the start of the next period of the following probing them 45150 When in one of the discretization elements the interference appears over the azimuth, in the first drive 9 in the sampling elements 1 and 2 (Fig. ) begins to accumulate a series of units corresponding to the threshold voltage exceeding the interference. When executed in the first decoder

1Q 11 of a predetermined detection logic (for example, a sequence of 5 units) at its output and, respectively, at the inputs of the first and second elements NAND 7 and 8, a discontinuity signal is produced (FIG. 3L), which allows updating of numbers in a reversible counter 3 each follow period. In this case, the maximum increase in the rate of increase in the threshold for example 2Q marriage (in this example, 6 times) before reaching the steady state.

when P 0.5 and both accumulators 9 and 10 do not provide permission signals. At the end of the azimuth

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25 2Q

25 2Q

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45

50

55

outputs (Fig. 3.6, c) of the synchronizer 6, so that before the beginning of the next period of the following probing them

The pulses of information from the last sampling element obtained in the previous period of the next one are in the time sampler 2, and in the penultimate cell of the N-ro register 14 shift, i.e. at the output of the memory block 13 and at the output of the code-voltage converter 5 (fig. 3 d), the information corresponding to the n-th discretization element is found. The last cells of the shift register 14 of the memory block 13 connected to the installation inputs of the reversing counter 3 (Fig. 3m) contain the number corresponding to the threshold level developed for the (n-l) -ro discretization element for all previous pulse repetition periods. With the first pulse (Fig. 36), the information from the first output of the synchronizer 6 advances and at the first output of the memory block 13 a number corresponding to the first sampling (Fig. 3g) occurs at the first output, and the number of the corresponding inputs 3 of the reversing counter 3 appears corresponding to the nth step (Fig. 3m). On the zero level (fig. Sv) of the first pulse from the second output of the synchronizer 6, the number g corresponding to the n-th discretization element is set in the reverse of the counter 3. By the positive differential at the subtracting input of the reyser counter 3, this number is reduced by one (), creating an updated Q number that with the arrival of the second pulse (FIG, ZB) from the first output of the synchronizers 6 is entered into the memory block 13. At the same time, at the outputs of memory block 13, codes of numbers appear, corresponding to the following samples.

For the following pulses (Fig. 3b, c) from the first and second outputs of the synchronizers 6, the cycle of operation of the proposed device is repeated for other pairs of sampling cells.

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The first and second drives 9 and 10 (figure 2) work as follows.

At the beginning of each sampling element from the output of the multichannel shift register 18, the accumulated sum of exceedances (Fig. 3 m) in the preceding sampling element (for the first accumulator 9) is sent to the installation inputs of the counter 15. The permission to write the number to the counter 15 is provided by a pulse (FIG. 3B) of the zero logic level. If in the current sampling element the excess is observed again (FIG. 3), then the number in counter 15 is increased by one for the positive differential of pulses on the counting input of counter 15 (similarly to FIG. 3 n). If there is a failure, then such a signal after integration in interval 16 causes reset of counter 15. The updated number from counter 15 is written to the -multi-channel shift register 18 by the nearest positive differential in the pulse sequence (FIG. 3 b) from the first output of synchronizer 6.

The word width in the multichannel shift register 18 is determined by the length of the accumulated series and is determined by the ratio

Q g p 25.

40

m - logj N -M ,,

where is the nearest greater integer value; N is the length of the accumulated series. The processes at the inputs and outputs of the first and second drives 9 and 10 must be in sync. For this, the delay introduced by the multi-channel shift register 18 must be equal to the follow-up period, as well as the delay created by the inter-input memory 13 and the output of the reverse information counter 3.

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Claims (1)

The correct functioning of the proposed device is provided by a temporary combination of all processes. The number of cells N in the shift registers 14 should be coupled with the number of pulses at the first and second outputs (Fig. 3,6, c) of the synchronizer 6 so that before the start of the next period of the pulse probes probing them fi, information from the last sampling element obtained in the previous period, is located in the time sampler 2, and in the penultimate cell N-ro of the shift register 14, i.e. at the output of the memory unit 13 and at the output of the code-voltage converter 5 (Fig. 3 g), there is information corresponding to the ηth sampling element. In the last cells of the shift registers 14 of the memory unit 13 connected to the installation inputs of the reverse counter 3 (Fig. 3 m), there is a number corresponding to the threshold level developed for the (n-1) th sampling element for all previous pulse repetition periods. With the first pulse (Fig. 36), information is promoted from the first output of synchronizer 6 and a number corresponding to the first discrete appears on the first output of memory unit 13 (Fig. 3d), and a number corresponding to the nth disc appears on the installation inputs of the reverse counter 3 (Fig. 3M). At the zero level (Fig. Sv) of the first pulse from the second output of the synchronizer 6, the number g _h corresponding to the ηth sampling element is set in the reverse counter 3. According to the positive difference at the subtracting input of the reversible counter 3, this number decreases by one (g _h ~ 1), creating an updated number Q _n , which, with the arrival of the second pulse (Fig. ST) from the first output of synchronizers 6, is input into the memory unit 13. At the same time, at the outputs of the memory unit 13, codes of numbers appear corresponding to the following discretes. According to the following pulses (Fig. 3 b, c) from the first and second outputs of synchronizers 6, the operation cycle of the proposed device is repeated for other pairs of discretization cells. The first and second drives 9 and 10 (figure 2) work as follows. At the beginning of each discretization element, from the output of the multichannel shift register 18, the accumulated sum of excesses (Fig. 3 m) in the preceding discretization element θθ (for the first drive 9) is received at the installation inputs of the counter 15. Permission to write a number to the counter 15 is provided by a pulse (FIG. 3b) of a zero logic level. If an excess is again observed in the current sampling element ₁₅ (Fig. 3g), then the number in the counter 15 increases by one by the positive pulse difference at the counting input of the counter 15 (similar to Fig. 3 and). If 0 0 does not exceed, then such a signal after integration in the interval 16 causes the counter to zero 15. The updated number from counter 15 is rewritten into a multi-channel 25 displacement histogram 18 with the nearest positive difference in the pulse sequence (Fig. 3 b) from the first output of synchronizer 6. The word length in the multichannel 00 shift register 18 is determined by the length of the accumulated series and is determined by the ratio w - 1 log, N [+1, 35 ' ^L where] · [is the next largest integer value; N is the length of the accumulated series. The processes at the inputs and outputs of the first and second drives 9 and 10 must be in phase. For this, the delay introduced by the multi-channel shift register 18 should be equal to the following period, as well as the delay of 45 liters created by the memory unit I3 between the input and output of the information of the reverse counter 3.