SU1336239A1 - Multichannel analog-to-digital converter - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in interface devices of digital computers, information exchange, measuring complexes of scientific research and control of technological processes. The aim of the invention is to increase the reliability by simplifying the device and expanding the field of application due to the possibility of obtaining output signals in a sequential code. A device containing a generator 1, a pulse counter 2, a register 8, a trigger 11, a digital-to-analog converter 14, a threshold element 22, an OR element 23, two counters 3 and 4 pulses, an operational memory 5 and 6, a multiplexer 7, And 9 elements are introduced and 10, triggers 12 and 13, switch 15, decoder 16, delay element 24, elements 3 AND-OR 25 and 2 AND-OR 26. 3 Il. S (L with so O5 y so with

Description

The invention relates to automation and computer technology and can be used in interface devices of digital computers, information exchange, measuring complexes of scientific research and control of technological processes.

The purpose of the invention is to increase the number of 1 trigger 12, the cycle of zeroing RAM 5 ends and the cycle of input and conversion of input information from bus 17 to information inputs of switch 15 begins. At the outputs of counters 2-4, a monotonically increasing code appears under the influence of generator 1 pulses. On reliability, by simplifying the device Q outputs of the decoder 16, the extension of the field of application for the signals distributed in time is formed, due to the possibility of obtaining output signals arriving at the control inputs of the signals in the serial code. mutator 15.

FIG. Figure 1 shows the function. In accordance with the data, the signal circuit of the multichannel analogue g at the input of the threshold element 22 of the digital transducer; Fig. 2 alternately switches the signals POS and 3, the timing diagrams of its operation.

Multichannel analog-to-digital converter contains generator 1, s

This voltage from the busbar 17. To the other input of the threshold element 22 a monotonously decreasing voltage is supplied from the output of the digital-to-analog converter 14, the value of which is proportional to the code from the output of the counter 4. At the same time the voltages at the inputs of the threshold element 22 are

first to third counters 2-4 pulses, the first and second operational storage devices 5 and 6, multiplexer 7, register 8, first and second elements And 9 and 10, from first to

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the third flip-flops 11-13, digital-analogue-25 its output signal 1 is generated,

switching trigger 11 to position 1. Signal 1 from the output of trigger 11 is fed to the input of RAM 5, the informational input of which is a serial exchange), bus 19. The end outputs signal 1 from the trigger output 12, and the words bus 20 output data - and to the address inputs - counter code 3,

corresponding to the number of the switched channel. At the same time, the signal 1 from the output of the trigger 11 permits the passage of the counter code 4 from the output of the multiplexer 7 to the information input of the RAM 6, and through the element 10 it allows the recording mode of the RAM 6.

The address inputs of the high-order bits of the RAM 6 receive the counter code 3 (channel number), and the address inputs of the lower bits - the counter code 2.

In addition, the control inputs of the multiplexer 7 receive the code of the 4g switch 2, under the influence of which the counter code 4 is switched at the information input of the RAM 6.

Thus, the counter 6, the value of which is proportional to 11, is written to the addresses of the corresponding codes of counters 2 and 3, and the value of the input voltage code from the output of counter 3 monotonously increases with address addresses. on one of the buses 17. The record information of the counter 3 corresponds to a bit as the number of channels of the input buses 17. Signal-1 of one bit. Upon completion of the recording of the overflow of counter 3, the word output at the overflow output through element 2И-OR 25 on counter 2 produces a pulse that plugs in the trigger input 11, and through which through element ZI-OR 25 after the delay element 24 - at the input it is set to the zero input of the trigger

converter 14, multichannel switch 15, decoder 16, input buses 17, first information output buses 18 (output parallel, second information output bus 21 (serial exchange output), threshold element 22, OR element 23, delay element 24, ZI elements- OR 25 and 2I-OR 26, bus 27 Start of data entry, bus 28 End of data output and bus 29 Reset.

The device works as follows.

In the initial state, the signal Reset counters 2-4, triggers 13 and 12 are set to O, and 11 g trigger to position 1. Under the influence of generator 1 pulses, a monotonically increasing code is generated at the outputs of counters 2 and 3. The JIH- formational input of the random access memory (RAM) 5 receives the signal O, and the input Record - signal 1 from the direct trigger output

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1 in flip-flop 12, endsAccording to these signals at the input of the threshold element 22, the signals are alternately switched

This voltage from the busbar 17. To the other input of the threshold element 22 a monotonously decreasing voltage is supplied from the output of the digital-to-analog converter 14, the value of which is proportional to the code from the output of the counter 4. At the same time the voltages at the inputs of the threshold element 22 are

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11, switching it to position O. Signal 1 from inverted trigger output 11 enters input Read RAM 5, Signal 1 is generated at output of RAM 5 at the moment when counter 3 emerges at the code corresponding to the channel number through which the input voltage has been converted in the code.

The signal 1 from the output of the RAM 5 prohibits the rewriting of the code in the RAM 6 during one conversion cycle, which eliminates the transformation ambiguity.

Similarly, input voltages from all buses 17 are converted into a code and recorded as bits in RAM 6. By the overflow signal of counter 4, trigger 13 switches to position 1 to generate a signal to begin output data at output 20. Signal 1 from the output of trigger 13 permits the passage of generator pulses to the input Read RAM 6 and the control input of the register 8. At the same time, the signal from the overflow output of counter 4 through the element OR 23 switches trigger 11 to position 1, and trigger 12 to position O. The data output and zero reset RAM 5 begins. impact By detecting the pulses of the generator 1 and the codes of the counters 2 and 3, the RAM 6 codes are read out simultaneously. At the same time, output 21 transmits data in the form of a sequential code.

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and on exit 18, in the form of a parallel code.

The serial code from the output of the RAM 6 is fed to the information input of the register 8, in which a bitwise shift of the input information occurs under the influence of the signals from the output of the AND 9 element. The signal from the overflow output of counter 2 fixes the end of the word output - output 19.

The signal from the overflow output of counter 3 through element 2I-OR 26 sets counter 4 and trigger 13 to position O, through element 24 of delay - trigger 12 to position 1, and through element ZI-IL 25 - trigger 11 to position O and goes to the output 28 End of data output.

Resetting RAM 5 occurs as described in the Initial State cycle. After this, a repeated data I / O cycle begins.

Thus, a multichannel analog-digital converter allows

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It greatly simplifies the design, expands the functions due to the possibility of exchanging with various subscribers in parallel and sequential codes.

Claims (1)

Invention Formula A multichannel analog-to-digital converter containing a pulse generator, an OR element, the first pulse counter, a digital-to-analog converter, input information buses, a threshold element whose output is connected to the synchronization input of the first trigger, a register whose outputs are the first information output buses, the bus data output, characterized in that, in order to increase reliability by simplifying the device and expanding the field of application due to the possibility of obtaining output signals in the code, the second and the third pulse counters, the first and second operational memories, the multiplexer, the first and second elements AND, the second and third triggers, the switch, the output buses, the output of the word and the output of the data, the second output information bus, the element delays, elements ZI-OR and 2I-OR, the decoder, the gate input of which is combined with the first input of the second element AND, is connected to the inverse output of the third trigger and is the bus Start of data input, and the information inputs of Rathore respectively combined with the address inputs of the first random access memory, the inputs of high bits of the address of the second random access memory and connected to data outputs of the second pulse counter whose count input is combined with the first input element strobiru- yuschim ZI-ISH1, podklto-, whose output to the overflow output of the first pulse counter is the bus. The end of the word output, the counting input of the third pulse counter is combined with the second gate input of the ZI-OR element, the input of the delay element, the first gate input of the II-OR element, and the overflow output of the second pulse counter and . is the output bus data, and the zeroing input of the third pulse counter is combined with the installation input in About the third trigger and connected to the output of element 2И-OR, the first information input of which is combined with the first information input of the element ZI-OR and connected to the inverse output of the second trigger, input setting 1 which is connected to the output of the delay element, and the installation input in O is combined with the installation input of 1 of the first trigger and connected to the output of the OR element, the first input of which is combined with the installation input of 1 of the third trigger and It is identical to the overflow ear of the third pulse counter, and the second input is ob7, it is single with the second information and gate inputs of the 2I-OR element and is a Reset bus, the second and third information inputs of the ZI-OR element are combined with the information input of the first operational memory device and connected to the direct output of the second trigger, and the third gate input element ZI-OR is connected to the output of the first random access memory, the read input of which is connected to the inverse output of the first trigger, and stroke entry is combined with a strobe input of the multiplexer, the second input of the second AND gate and is connected to the forward the output of the first trigger, the installation input of which is connected to the output of the ZI-OR element, the information the input is a logical GG 1 bus, the first input of the threshold element is connected to the switch input, and the second input is connected to the output of the digital-analog converter, the inputs of which are respectively connected to the information inputs of the multiplexer and connected to the corresponding information outputs of the third counter, and the control inputs the multiplexer, respectively, combined with the inputs of the lower bits of the address of the second random access memory and connected to the corresponding information outputs of the first account pulses, the counting input of which is combined with the first input of the first element I and connected to the output of the pulse generator, and the second input of the first element I connected to the forward output of the third trigger and is the bus Start of data output, the control input of the register is combined with the input Read the second memory device and is connected to the output of the first element And, and the output of the second element And is connected to the input Record of the second memory device, the information input of which is connected to the output of the multiplexer, and The output is connected to the information input of the register and is the second output information bus, the outputs of the decoder are connected respectively to the control inputs of the switch, the information inputs of which are information buses. fl jnj lJlJlJlJn nJlJlJlJlJTJ4J rLn 6 JLJLJLJLJLJLJL 6I1IL r - TT R one  -} Editor A. Vorovich Order 4055 / 56Type Qniт Subscription VNSHSHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project T Compiled by Yu. Spiridonov Tehred And Popovich Corrector. Shekmar