SU1336220A1 - Voltage level digitizer - Google Patents

Abstract

The invention can be used to build devices for analyzing input signals. The voltage level sampler contains comparators 1, 5, input voltage source 2, resistors 3, 7, 10, reference voltage source 4, capacitors 6, 8, D-flip-flop 9. The invention expands its functionality by ensuring that the output voltage is once signal with a pulsed input voltage. 2 Il. Ibykh SL OO SL 05 GCHE N3. one

Description

The invention relates to a pulse technique and can be used in the construction of devices for analyzing input signals.

The aim of the invention is to enhance the functionality by providing a single formation of the output signal with a pulsating input voltage.

FIG. Figure 1 shows a block diagram of a voltage level sampler; in fig. 2 - time diagrams of his work.

The voltage level sampler contains the first comparator 1, the first input of which is connected to the source 2 of the input voltage, and the second input through the first resistor 3 to the source 4 of the reference voltage, the second comparator 5, the non-inverting input of which is connected to the source 2 of the input voltage, and the non-inverting input is connected via the first capacitor 6 to the zero potential bus, via the second resistor 7 to the output of the second comparator 5 connected via the second capacitor 8 to the clock input of the D-flip-flop 9, the information input of which connected to the output of the first comparator 1, and an output connected via third resistor 10 to the noninverting input of the first comparator 1.

The device works as follows.

If the voltage at the inverting input of the first comparator 1 is less than the voltage at its non-inverting input, then the voltage at the output of the first comparator 1 is equal to a logic zero and the voltage at the output of the D-flip-flop 9 is also zero.

At time t, (Fig. 2), the voltage at the inverting input of the comparator 1 exceeds the voltage at its non-inverting input and the voltage corresponding to a logical one is formed at the D input of the D-flip-flop.

However, the D-flip-flop does not change its state, since it is set so that its operation occurs on a positive voltage drop across the clock C-input.

A positive voltage drop at the clock C input is generated again when the voltage 0 of the input voltage 2 of the input voltage becomes less than the voltage on the capacitor 6, i.e., at the moments when the voltage UBX decreases, because positive is formed

0

five

the voltage from which the discharge of the capacitor 6 occurs through the resistor 7.

At the time ti (Fig. 2), the positive voltage drop across the clock C input and the logical unit at the D input of the D flip-flop 9, which is triggered, and at its output, the voltage will be equal to the logical one that does not change upon return comparator 1 to its initial state for a time shorter than the time between the maximum peaks of the pulsating voltage of the source 2 of the input voltage.

D-trigger 9 returns to original

state at time tj, (fig. 2)

the coincidence of the peak of the pulsating voltage5 and the absence of voltage at the D input.

At the output of the D-flip-flop 9, the output voltage from the output of the divider, for example, is set to minus 0.5 V, which, after a D-flip-flop 9 triggers from the output of which the positive polarity is formed, becomes, for example, minus 0.4 V which is an added advantage of the proposed level discretization.

By performing a voltage setting on the voltage divider on the resistors connected between the voltage source 4 and the output of the trigger 9, you can set any hysteresis to trigger the level sampler.

Claims (1)

Invention Formula A voltage level sampler containing a comparator, the first input of which is connected to the input voltage source, and the second input - to the reference voltage source, a resistor, characterized in that, in order to extend the functionality due to the single formation of the output signal with a pulsing input voltage, it introduced the second comparator, D-flip-flop, the first and second capacitors, while the first terminal of the resistor is connected to the inverse of the second comparator connected through the first schine capacitor to ground potential, and a second terminal connected directly to the output of the second comparator and is connected via a second capacitor to the clock input of D-flip-flop having an information input coupled to an output of the first comparator, the non-inverting input of the second comparator is connected to a source of input voltage. 0 five 0 five 0  Lj l 1Л6ых tz FIG. 2