SU1335976A1 - Device for determining analog-signal extreme values - Google Patents

Abstract

The invention relates to information processing and storage systems, in particular extreme values of parameters, and can be used in devices for amplitude measurements in mechanical engineering. The device contains a shaper 1 codes, elements AND-NOT 2,3, counters 5, 6, triggers 7,12 shaper 4 pulses, elements OR-NOT 9 and 10, NOT 11, integrating the RC-chain 8. Shaper codes, representing itself The ADC of push-pull integration generates output codes proportional to the direct and additional codes of the analog signal. When counting the number of pulses proportional to these codes, the counters select signals proportional to the maximum and minimum values of the analog signal and their difference. 4 il. with (L

Description

The invention relates to information processing and storage systems, in particular Extreme parameter values, and can be used in devices for amplitude measurements in mechanical engineering.

The purpose of the invention is to expand the scope of application by fixing the maximum value of the signal.

FIG. 1 shows a functional diagram of the device; in fig. 2-4 - timing charts of the device. .

The device contains a shaper 1 codes, elements AND-NOT 2 and 3, shaper 4 pulses, counters 5 and 6, trigger 7, as part of a pulse shaper - integrating RC-chain 8, element AND-HE 9, element OR 10, element 11 , trigger 12, element And 13, element W-NOT 14, element AND 15, element NOT 16.

The device works as follows.

In the initial state, when there is a zero voltage level on the control bus, there are 1 direct codes on the direct and additional codes of the driver (according to Fig. 4), having installed the Front on their counting inputs. Single voltage levels follow, which form a zero level at the output of the AND-NOT 2 element. As a result, both triggers 7 and 12 are set to the zero state. Counters 6 and 5 are set to zero at a unit level on their R input. In the initial state, the counter 6 will be set to zero, since a unit level is formed at the output of the element AND 1 1, and the counter 5 is set to the single state. At the same time, zero voltage levels are set on the output buses of the minimum, maximum, and delta codes. At the time the device starts up, a single

trigger 12 is switched to one state, i.e. at its inverse vy course, a zero level will be established, which will form a single voltage level at the output of OR-NOT 14. And this level will keep the counter 5 in zero, at the moment t ,, when the voltage is switched from the zero level to the unit on the direct code bus, the pulse driver, which is from the element OR 10, the first element AND 11 is the time setting RC - chains of 8 and the third element, AND-HE 9, will form at the output of the element And 11 a short positive impulse, which

4Q P1 will set counter 6 back to zero. The counter 5 sets the zero state at its outputs, i.e. during the course of its higher discharge, the voltage level is switched from one to zero. As a result

the voltage level that allows the driver 1 codes. The latter is a push-pull ADC; its sleep time (from the graphs in FIG. 4) The input signal is integrated into the ADC over time; from time t to time t, integration of the reference voltage of opposite polarity. This MO is the time of the forward bus the code forms a negative pulse

55

standing on the R input until the voltage level on the direct code bus switches from zero to one.

Consequently, by the time of forming the zero level on the bus, the additional length (L –t) is proportional to the input signal at the given sampling time. From the moment t to the moment t, a negative impulse of duration (t, t ,,) is also formed on the additional code bus. With this, (,) -b. (T, -t)

 t -t - t -t M 3. about

At time t, the first MS transformation cycle ends, and the second begins, and so on.

At time t, i.e. with the arrival of the zero level on the direct code bus

A single level is formed at the input of the NANDEM element 2, at its output, which will allow 3 high frequency pulses from the clock output of the driver to pass through the NAND element. These pulses arrive at the counting inputs of both counters 5 and 6. The capacity of each counter is equal to N pulses. And since during the time (,) the formation of the direct code in the counter

6 will pass the number of pulses less than N, so the counter 6 will not overflow by the time t and the trigger 7 will not change its state. Both triggers 7 and 12 change their state on the back

Front for their counting entries. Sledo-

at the time t ,, when the voltage is switched from the zero level to a single one on the direct code bus, the pulse driver, which is from the element OR 10, the first element AND 11, is the time specifying the RC circuit 8 and the third element AND - NO 9, will form at the output of the element 11 a short positive pulse, which will set the counter 6 again to the zero state. The counter 5 sets the zero state at its outputs, i.e. during the course of its higher discharge, the voltage level is switched from one to zero. As a result

55

standing on the R input until the voltage level on the direct code bus switches from zero to one.

Consequently, by the time of forming the zero level on the additional code bus (t in Fig. 4), both counters 6 and 5 are zero. The additional code in the first conversion cycle is recorded in both counters 6 and 5 and stored in them until the arrival of the direct code in the second conversion cycle (code b in Fig. 2). Since b a is, then when writing b code to counter 6, the counter will overflow, and after overflow, the difference (b-a) will be written to it. When the counter 6 overflows, the trigger 7 switches to the one state and therefore, at the end of the zero level on the direct code bus, the setting pulse at the output of the first element And 11 is not formed and the counter 6 is not reset. And this means that the additional code (N-b) of the second conversion cycle is added in counter 6 with the difference b stored there (Fig. Pro):

(N-b) + (b-a) N-a,

Similarly, in the third cycle, the stored difference (N-a) is added first with, and then (N-c), T.e. at the time of the end of the recording, in the counter 6 of each successive additional code (N-i) formed in the increase portion of the input signal and in the decrease portion not exceeding the increase span, the supplementary code of the minimum input signal is stored in the count 6.

When writing to the counter 6 of the code e, which is less than a, the counter overflow will not occur:

(N-a) + e, since a with,.

Triggers 7 and 12 are set to zero by the R inputs in each conversion cycle at the time of integrating the ADC of the input signal. Consequently, at the moment of termination of the zero level of the code e, the trigger 7 remains in the zero state, and a short positive pulse is generated at the output of the first element 11 and sets the counter 6 to the zero state. After that, an additional code of the smallest signal value (N-e) will be recorded in counter 6 and will be stored there dynamically, similarly to the previously stored code (N-a). In counter 5 to the counting input do the same

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direct and additional codes, as to the input of counter 6, but due to a different switching circuit, counter 5 dynamically stores the additional code of the maximum signal value. The processes occurring in counter 5 are shown in FIG. Zb. As already noted, in the initial state, the counter 5 is in the state of the maximum number at its outputs. Consequently, with the arrival of the first pulse of the code at its counting input, the voltage level at the high-end output of the counter switches from one to zero, and the trigger 12 is switched to one state. As a result, the zero level at its inverse output forms at the output of the element OR NOT 14 a single level that keeps the counter 5 in the zero state until the end of code a. After that, the code (N-a) will be recorded in counter 5. Next to the code (Na) dose-5, the code b is written, and since b a, then when recording b, counter 5 will again overflow, which will switch trigger 12 and again block counter 5 through the element OR NOT 14 to the zero state before the end My code b. At the end of code b, the lock is released, and an additional code of a higher number (N-b), etc., is written to counter 5. After the direct code, counter 5 will record and the N-C code will be stored. And at the moment of the end of the recording of the code (N-d) and (N-e) the code N-c will be stored in the counter;

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five

40

(N-c) + d + (N-d) + e + (N-e) (N-c) + 2N,

those. Two overflows will occur, and the contents of the counter at the time of termination of the additional code (N-e) will be 45 (N-c). With the arrival of a larger code k, the lock will work again. And at the end of k, the code (N-k) will be recorded in counter 5 and will be stored dynamically similarly to the previously stored

50 code (N-C).

Consequently, proceeding from the graphs of the processes in the counters shown in FIG. 36 and 36, it can be concluded that the direct code of the minimum value of the input signal can be selected in any ADC conversion cycle during the formation of each direct code until overflow.

counter 6. This is provided by the element OR 10 and element 16. The direct code of the maximum input signal can also be selected in any ADC conversion cycle from the beginning of the direct code and until the counter is full 5. This is provided by element 13. Because the beginning of the formation of the minimum and maximum codes are the same, the difference code can be selected with the help of the element 15. Thus, we obtain positive impulses on the buses of the minimum, differential and maximum codes, the duration of which is ortsionalny corresponding to values of the input signal.

Formula inventions

A device for determining extreme values of an analog signal, comprising a code generator, first and second AND-NES elements, first and second counter, trigger, AND element, pulse shaper, including OR element, integrating RC chain, AND-N element, and AND element, the input of the code generator is the input of the analog signal of the device, the output of the additional code generator code is connected to the first input of the first NAND element, the second input of which is connected to the output of the direct code generator code and to the first the moves of the OR and AND elements of the pulse maker, and the output is connected to the first input of the second NAND element, the second input of which is connected to the clock output of the code generator, and the output is connected to the counting input of the first counter, the overflow output of which is connected to the trigger synchronous input, direct output which is connected to the second input of the OR element, the output of which through the integrating chain

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five

connected to the first input of the pulse generator NAND element, the second input of which is connected to the start of the code generator cycle output, and the output is connected to the second input of the And pulse generator element, the output of the pulse generator, is connected to the installation input of the first counter zero, characterized in that In order to expand the field of application due to the possibility of fixing the maximum value of the signal, the output of the element And the pulse former is the output of the pulse former, two output elements are introduced into the device and AND, OR-NO element, the second flip-flop and two NOT element, wherein the beginning of the output; the code generator cycle through the first element is NOT connected to the installation input to the single state of the second counter, the counting input of which is connected to the output of the second element 5 IS-NOT, and the overflow output is connected to the synchronous input of the second trigger, the installation input to zero of which is connected to the output of the first element AND-NOT, the installation input to zero of the first trigger and the first input of the first output element AND, the second input of which is connected to the inverse output of the second trigger and the first, the input of the OR-NOT element, the second input of which is connected to the output of the direct code of the generator of codes, and the output is connected to the input of setting the zero state of the second counter, the output of the first output element AND is the output of the maximum signal of the device and connected to the first input of the second output element AND whose output is the output of the difference value device, and the second input is connected to the output of the OR element and the input of the second element NOT, the output of which is the output of the minimum signal value of the device.

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Editor N.Egorova

Compiled by E.Ivanova Tehred M.Hodanich

Order 4048/43 Circulation 672 Subscription

VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035

Production and printing company, Uzhgorod, st. Project, 4

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Proofreader I. Muska

Claims (1)

Claim A device for determining extreme values of an analog signal, comprising a code generator, first and second AND-NOT elements, a first and second counter, trigger, AND element, a pulse generator, including an OR element, an integrating RC chain, an AND-NOT element and an AND element, moreover, the input of the code generator is the input of the analog signal of the device, the output of the additional code of the code generator is connected to the first input of the first AND-NOT element, the second input of which is connected to the output of the direct code of the code generator and to the first input of the elements of the pulse shaper OR and AND, and the output is connected to the first input of the second AND-NOT element, the second input of which is connected to the clock output of the code shaper, and the output is connected to the counting input of the first counter, the overflow output of which is connected to the trigger sync input, whose direct output connected to the second input of the OR element, the output of which through an integrating chain is connected to the first input of the AND-element of the pulse shaper, the second input of which is connected to the output of the beginning of the cycle of the code shaper, and the output is Inonii to a second input of the AND of the pulse, the pulse shaper output is connected to the zero setting input 10 of the first meter, characterized in that, in order to expand the scope of application due to the possibility of fixing the maximum signal value, the output of the And15 element of the pulse shaper is the output of the pulse shaper, two output elements And, an OR-HE element, a second trigger and two elements are NOT, and the output at the beginning of the cycle of the code generator through the first element is NOT connected to the unit input to the unit state of the second counter, the counting input of which is connected to the output of the second element 25 AND NOT, and the overflow output is connected to the sync input of the second trigger, the zero input of which is connected to the output of the first AND-NOT element, the zero input of the first 30 trigger and the first input of the first And output element, the second input of which is connected to the inverse output the second trigger and the first input of the OR-HE element, the second input of which is connected to the direct code output of the code generator, and the output is connected to the zero input of the second counter, the output of the first output element AND 4Q is the output of the maximum value of the signal of the device and is connected to the first input of the second output element AND, the output of which is the output of the value of the difference of the device, 45 and the second input is connected to the output of the OR element and the input of the second element NOT, the output of which is the output of the minimum signal value of the device. Fi g. 2 Cz —Mc -> N a. I -4 = Η · --1 ^{N c} US Λ -1 N 1 J 1 f ^₽ 1 Hf | *4 | e ^R n Af 1,1 * - “J N SiS Si— C6pot P * p a I