SU1334376A1 - Signal converter - Google Patents

Abstract

The invention relates to automation and can be used to connect analog and digital sources with digital computing devices. The invention makes it possible to eliminate the effect of systematic errors in reading information, thereby increasing the accuracy of the signal converter. The signal converter contains an inverter 1, two formers 2 and .3 pulses, two formers 4 and 17 unit increments, each of which contains two blocks 5 and 6 of memory and a decoder 7, four elements AND 8-11, five IDN elements 12 - 16 and counter 18 pulses. 1 il. Z i 26 25 (L from 00 4 00 h about:

Description

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The invention relates to automation and can be used to communicate analog and digital information sources with digital computing devices.

 The aim of the invention is to improve the accuracy of the converter by eliminating systematic errors in reading information.

The drawing shows the functional diagram of the device.

The signal converter contains an inverter 1, the first 2 and second 3 pulse shapers, the first driver 4 unit increments, consisting of the first 5 and second 6 memory blocks and the decoder 7, the first - the fourth elements AND 8-11, the first - the fifth elements OR 12 - 16, the second driver 17 unit increments and the counter 18 pulses.

In the drawing, reference numerals 19-21 denote, respectively, the first and second information and clock inputs of the converter, and positions 22-26, respectively, the first - fifth outputs of the converter.

The signal converter works as follows.

The formers 2 and 3 give out pulses that are shifted relative to each other in one of two directions, which corresponds to 1 and O. The pulses from formers 2 and 3 that are shifted relative to each other are considered as numerical ratios O, 1, 2, J 3 O and O, 3, 2, 1, O, one of which is taken as 1, and the second as O. Such pulses are on the driver. 2 and 3 can be obtained by reading two sensitive elements, shifted relative to each other, information from a code element, or by receiving pulses that are shifted relative to each other via two communication channels.

The output state, for example, driver 2 is characterized by two possible voltage levels, and the number of level combinations on two driver 2 is four, which in binary code look like 00, 10, 11, 01, or O, 1, 2 3. Provided that the information and) m-pulses at the outputs of the formers 2 and 3 are shifted relative to each other by half the pulse duration, then when receiving the information pulse

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The state of the output drivers 2 and 3 always change in the specified order of 00–10–11–01–00 for 1 and in the order 00–01–11 - 10 - 00 for O. Each of these transitions between two Neighboring numbers are said to be single and are characterized by a change in the state of the spin of only one of the formers, while the output state of the other is unchanged. The shaper 4 unit increments generates for each unit increment one and only one pulse at one of its outputs, depending on the sign of the unit increment.

The current signal from driver 2 and 3 is compared with the previous current signal, which is recorded in driver 4 (in memory block 6). If these signals differ from each other by a single increment, then, depending on its sign, shaper 4 produces a pulse at one of its outputs. The duration of this pulse coincides with the duration of the clock pulse at the input 21. The pulses of single impulses during counting are counted by a reversible counter 18 taking into account their sign. When receiving. 1, four impulses of positive unit increments are received at the input of the summation of counter 18, and when receiving O, four impulses of single negative increments are sent to the subtraction input of counter 18. With the help of elements 8-15, the moments of passing the counter 18 numbers, multiples of four: O, 4, 8, 12, which constitute the second numerical series, are sequentially allocated. Considering the transitions between the numbers of the second row single, the former 17 produces pulses of one for the second row, where the pulses of positive and negative increments are equivalent to received 1 and О, respectively. The signals from elements 8-15 are distributed over the inputs of block 5 of the forwarder 17 so that the same code as that used in the former 4 is obtained at its outputs. This allows representing transitions by means of O, 4, 8 sums 12 as single ones and form on the former 17 for each such transition a single increment pulse positive for received 1 and negative for

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O .. The pulses at the outputs 22-26 do not depend on the number of received interference pulses.

The signal converter is insensitive to short-term interference of any kind, which is less than half the duration of the information pulse. For example, an interference pulse on one of the formers 2 and 3 is perceived as two transitions from the number O and 1 and back from 1 to O, which are generated by the shaper 4 two impulses of unit increments of opposite signs, while on the counter 18 is the number adjacent to O and a multiple of four will not be achieved and no changes will occur on the second outputs 24-26.

In another case, the synchronous occurrence of pulses, for example, from an atmospheric electromagnetic pulse, on the former 2 and 3 is perceived as a transition from O to 2 and back from 2 to O. Such transitions are not single increments and are not perceived by the former 4.

Long impulses of interference can be superimposed on shorter impulses of information, which leads to their loss against the background of an interfering impulse; In this case, the converter does not reproduce either 1 or O, at the place of which there will be a space in the chain of binary signals of the transmitted word.

Claims (1)

Invention Formula A signal converter comprising an inverter, the input of which is a clock input of the converter, first and second pulse shapers, the inputs of which are respectively the first and second information inputs of the converter and the first unit increment generator containing the memory blocks and the decoder, the first and second outputs of the first block memory connected. Respectively with the input and decoder of the same name and the second memory block, the first and second outputs of which are connected respectively with the third fourth inputs of the decoder, the first 6 the primary and second inputs of the first memory block of the first shaper unit of increments are connected to the outputs of the first and second pulse shapers, respectively; the clock inputs of the first and second memory blocks of the first generator of single increments are connected respectively to the input and output of the inverter, the first and second outputs of the decoder of the first unit increment generator are the first and second inputs of the converter, respectively, so that, in order to increase the accuracy of the converter by eliminating systematic read errors, elements are entered into it And, OR elements, the second unit increment shaper, made similar to the first unit increment shaper, and the pulse counter, the outputs of the first and second bits of which connected to the first and second inputs of the first, second, third and fourth elements, respectively; the first and second outputs of the third discharge of the pulse counter are connected to the third inputs of the first, third and second, fourth And elements, the first and second outputs of the fourth bit of the pulse counter, respectively, are connected to the fourth inputs respectively, the first, second and third, fourth elements And, the output of the first element And connected to the first inputs of the first and second elements OR, the outputs of which are connected to the same inputs of the first memory block of the second unit increment generator, the output of the third element And connected to the first inputs of the third and fourth element OR, the outputs of which are connected to the same inputs of the first memory block of the second single increment generator, the output of the second element I is connected to the second inputs of the second and the third element OR, the output of the fourth element I is connected to the second inputs of the first and fourth elements OR, the first and second inputs of the pulse counter are connected respectively to the first and second outputs of the decoder of the first single increment generator, clock inputs of the first and second memory blocks of the second single constituent 5 13343766 increments are combined with the same names to the first and second clocks of the same input blocks of the fifth OR element and are the memory of the first one-with the third and four-time increments, the first and second high outputs of the converter, the output of the decoder of the second form; that OR element is the fifth unit increment body connected to the output of the converter.