SU1328942A1 - Syncro generator - Google Patents

Abstract

The invention relates to still image transmission means and provides an increase in the accuracy of the sync signal formation. The device contains a tag recorder 1, trigger 2, a pulse frequency divider 4 containing a counter 5 and a decoder 6. Two generators of 3 and 12 pulses are newly introduced and a switch 7 containing elements AND 8 and 9, inverter 10 and element OR 11. 1 C .Pa f-ly, 2 IL. Fig: 1

Description

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This invention relates to the transmission of Fixed Images and can be used in synchronization systems for scanning devices.

The purpose of the invention is to improve the accuracy of the formation of the clock signal.

Figure 1 shows the electrical block diagram of the synchro generator; FIG. 2 shows timing diagrams explaining his work,

The clock generator (FIG. 1) contains the recorder 1 tags, trigger 2, the first generator of 3 pulses, the divider 4 pulse frequency, containing counter 5 and decoder 6, switch 7 containing the first 8 and second 9 Elements AND, inverter 10 and OR 11. the second generator 12 pulses

Sync generator works as follows

In the initial state, counter 5 and trigger 2 are reset. Consider the operation of the device under conditions when the distance between two adjacent labels is equal to the average calculated.

Impulse Tag, coming from the output of recorder 1 (FIG. 2a) to the first (counting) input of trigger 2, the potential drop from the level of the logical unit to the level of logic zero sets the latter to the state of the logical unit (FIG. 26). the first input of the switch 7, t, e, if there is a logical zero level on it and if there is a logical unit level at the second input of the switch 7, the second input of the counter 5 from the output of the switch 7 receives pulses from the output of the first generator 3 (FIG. 2c) At the output of the descrambler Oral 6 selects the pth pulse from the pulse sequence fed to the input of counter 5, which goes to the second (reset) input of trigger 2 and determines the end of the resolution of the passage of frequency pulses from the output of the first generator 3 through the switch 7 (FIG. ). In this case, a group of n pulses goes to the output of the device from the output of the switch 7 (FIG. 2e). Further, the process of forming groups of n pulses repeats with the arrival of each pulse. Mark, Reset of the counter 5 is performed by the Gg-th pulse coming from the decoder. b to the entrance of the counter 5

28942 2

Suppose a sharp movement of the carriage leads to a significant decrease in the distance between two adjacent marks. Since the frequency of the pulses of the first generator 3 is selected on the basis of the average distance between the marks, n pulses of this frequency do not fit in this case the current between two adjacent marks in the IQ period. To ensure the accuracy of the sweep, the passage signal is transmitted to the first and second inputs of the switch 7. high frequency from the progress of the second generator 1 2 (fig, 2d) through the switch 7 to the input of the counter 5, the decoder 6 waits on the input, the nth pulse from the sequence of pulses coming from the output of the first 2Q generator 3, pulses from the output of the second generator 12 and supplementing the group of pulses up to the number n, which are

25 arrive at the output of the device.

Invention Formula

Claims (1)

1, a sync generator containing 30 tag recorder, trigger and pulse frequency divider, characterized in that In order to improve the accuracy of the formation of the sync signal, the first pulse generator and the switch are connected in series, the second input of which is connected to the trigger output, the first and second inputs of which are connected respectively to the otter with a pulse frequency divider and pc of the tag mastercord, the third input is combined with the second input trigger, and the output is connected to the input of the pulse frequency divider,. as well as the second pulse generator, the output of which is connected to the fourth input of the switch, 2, The clock generator of claim 1, 1, and τ is gg in that the switch is made in series of the first AND element, the first and second inputs of which are respectively the first and second inputs of the switch, and the OR element whose output is output of the switch, the second element And, the first input of which is combined with the second input of the first element And, and the second 35 31328942 the input is the fourth input of the com switch input and is combined with the third input of the second element is And, and the output is connected to the third input mutator, and the output is connected to the second input of the OR element, as well as the inverter, whose input is the third of the first Element AND,  ABOUT t FIG.