SU1322450A1 - Device for measuring frequency deviation from rated value - Google Patents

Abstract

The invention can be used in the development of devices for receiving and processing a signal. The purpose of the invention is to increase the range of convertible frequencies. The device contains a counter 3 and elements AND 6, 9 and 10. A controlled oscillator 1, a control element 2, a phase register 4, a comparison block 5, a time interval trigger 7, delay elements 8, 16, 45 and 46, elements are entered into the device. OR 11, 34-36, 1 lines 12, 13 and 44 delays, control triggers 14 and 15, drivers 17 and 18, analysis register 19, modulo-20.1-20.jV circuits, And 21, 37 and 38 elements, inverters 22 and 23, delay selector register 24, encoder 25, trigger 26 "More, trigger 27" Less, switching unit 28, comparators 32 and 33 frequencies, register 39 cycles, register 40 rezul acetate, the decoder 41, driver 42 and power level of the AND 43.1-43.YA and formed new functional bond. In the description there are diagrams of a decoder 41, a shaper 42 and a comparators 32 and 33 frequencies. 3 h. the item of f-ly, 7 ill. SL 00 IND ьo 4 SL bydoca reza / otat SroiT

Description

The invention relates to a measurement technique and can be used in the development of devices for receiving and processing a signal.

The aim of the invention is to increase the range of convertible frequencies.

FIG. 1 shows the electrical functional scheme of the device; in fig. 2 - electrical functional decoder circuit; in fig. 3 — electric schematic diagram of the level generator; in fig. 4 - electric functional frequency comparator circuit; in fig. 5 is a plot of the phases of various signals versus time, explaining the operation of the device; in fig. 6 and 7 are timing diagrams that illustrate the operation of the comparator.

The device contains a controlled oscillator 1, a control element 2, a counter 3, a phase register 4, a comparison block 5, the first AND 6 element, a time interval trigger 7, the first delay element 8, the second 9 and third 10 AND elements, the first OR 11 element, the first 12 and second 13 delay lines, the first 14 and second 15 control triggers, the second delay element 16, the first 17 and second 18 drivers, the modulation analysis register 20.1-20.p modulo two, the fourth And 21 element, the first 22 and second 23 inverters, delay selection register 24, first encoder 25, first trigger 26 " Longer, the first trigger 27 "Less, switching unit 28, which consists of elements AND 29.1-29.p and second 30 and third 31 elements OR, first 32 and second 33 frequency comparators, fourth 34, Fifth 35 and sixth 36 elements OR , fifth 37 and sixth 38 And elements, register of 39 cycles, result register 40, decoder 41, shaper 42, block 43.1-43.p of And elements, third delay line 44, third 45 and fourth 46 delay elements.

The decoder 41 contains the element NOT 47, the first 48 and the second 49 decoders, the seventh-twentieth elements And 50-63. A shaper 42 of levels comprises fifteen circuits, each of which contains an amplifier 64, a first diode 65, a voltage divider 66, a second diode 67, in addition, a resistor 68 and a repeater 69 are included in the shaper 42 levels.

The frequency comparator contains the first 70 and second 71 registers, the second encoder 72, the second trigger 73 "More, the second trigger 74" Less.

Input "Start the device connected to the reset input register 40 of the result, the installation of the register register 39 cycles and the installation input of the trigger 7 time interval, the output of which is connected to the first input of the second element And 9 and the input of the first delay element 8, the output of which is connected to the reset input of the trigger 7 the time interval, the inverse output of which is connected to the first input of the second element And 10,

0

The second input is connected to the output of the second delay line 13, and the output is connected to the second input of the first element OR 11, the first input of which is connected to the output of the second element AND 9, the second input of which is the device input, the output of the first element OR 11 is connected via the first line 12 delays with the input of the second delay line 13 and the installation input of the first control trigger 14, the output of which through the second delay element 16 connected in series and the first driver 17 is connected to the reset input of the first control trigger 14 and the second entrances of p 37 and sixth 38 elements And, and through

5 the second driver 18 — with the fifth inputs of the first 32 and second 33 frequency comparators, the reset inputs of the first trigger 26 ”More and the first trigger 37” Less, and with the installation input of the second control trigger 15, the reset input of which is connected

0 with the clock inputs of the 4-phase register and the delay selection register 24, as well as with the output of the fourth element 21, and the output of the second control trigger 15 is connected to the third input of the fourth element 21 and 21,

r the second input of which is connected to the output of the first inverter 22. whose input is connected to the clock inputs of the counter 3 and the analysis register 19, the second input of the first element 6 and the output of the controlled generator 1, the input of which is connected to the output of the control element 2, whose input connected to the output of the level generator 42, the inputs of which are connected to the corresponding outputs of the decoder 41, the inputs of the first group of inputs of which are connected respectively to the first inputs.

5 elements AND block 43.1-43.p elements And and the corresponding outputs of the register 40 result.

The inputs of the second group of inputs of the decoder 41 are connected to the corresponding outputs of the register of 39 cycles, the output of which, corresponding to the first bit, is connected to the second inputs of the AND elements included in block 43.1-43.p And elements and is one of the outputs of the device together with the outputs of the block 43.1-43. The p elements I, n of the taps of the first delay line 12 are connected to the corresponding information inputs of the analysis register 19 and the second inputs of the corresponding elements 29.1-29.p included in the switching unit 28, the first inputs of which are pairwise

0 combined and connected to the corresponding inputs of the first group of inputs of the first encoder 25 and with the outputs of the register 24 of the delay selection, the information inputs of which are connected to the corresponding outputs of the circuits 20.1-20.

5 two and the inputs of the second group of inputs of the first encoder 25, the outputs “More and“ Less than which are connected respectively to the information inputs of the first trigger 0

pa 26 "More and the first trigger 27" Less, the outputs of which are connected respectively to the third input of the fourth element OR 34 and the second input of the fifth element OR 35, the output of which is connected to the nerve input of the sixth element And 38, the output of which is connected to the second input of the sixth element OR 36, the output of which is connected to the clock inputs of the register 39 cycles and the result register 40, whose information input is connected to the output of the fourth element OR 34 and the first input of the fifth element AND 37, the output of which is connected to the first input of the sixth element nta OR OR 36.

The outputs of the counter 3 are connected respectively to the inputs of the second group of inputs of the comparison unit 5 and information inputs of the phase register 4, the outputs of which are connected respectively to the inputs of the first group of inputs of the comparison unit 5, the output of which is connected to the first input of the first element 6 and whose output is through the second inverter 23 connected to the clock inputs of the first trigger 26 "More and the first trigger 27" Less, and directly to the input of the third delay line 44, whose K. of taps are connected to the inputs of the second groups of inputs of the first 32 and t 33 frequency comparators, and the output through the third delay element 45 - with the third inputs of the first 32 and second 33 frequency comparators, and through the third 45 and fourth 46 delay elements - with the fourth inputs of the first 32 and second 33 frequency comparators, the first inputs of which are connected respectively with the outputs of the second 30 and third 31 OR elements included in the switching unit 28. The inputs of the second element OR 30 are connected respectively to the outputs of the odd elements And 29.1-29.l, included in the switching unit 28, and the outputs of the even elements And 29.1-29.p - with the inputs of the third element OR 31, with the first outputs of the first 32 and the second 33 frequency comparators are connected respectively to the first and second inputs of the fourth element OR 34, and the second outputs of the first 32 and second 33 frequency comparators to the first and third inputs of the fifth element OR 35.

The output of the lower bit of the analysis register 19 is connected to the first input of the first modulo-two summing circuit 20.1 and the second input of the last circuit 20.n from the modulo-two summing circuits, the output of which is connected to the first input of the fourth element And 21. The remaining outputs of the bits The analysis register 19 is connected as follows: the output of the second bit is connected to the second input of the first circuit from the modulo-two summing circuits 20.1 and the first input to the second of the modulo-two summing circuits 20.2, the third-bit output is

0

five

0

five

0

five

0

five

0

five

with the second input of the second circuit 20.2 and the first input of the third circuit 20.3 modulo two, and so on, the most significant bit with the second input of the penultimate 20.1 - 1 and the first input of the last circuit 20.l summing over module two.

The first input of the first group of inputs of the decoder 41 is the input of the HE element 47, connected to the inputs A of the first 48 and second 49 decoders and the first input of the eighth element AND 51, the second input of which is the second input of the second group of inputs of the decoder 41 and connected to the second input of the seventh element 50, the first input of which is connected to the output of the element NOT 47, the second input of the first group of inputs of the decoder 41 are interconnected inputs B of the first 48 and second 49 decoders, and the third input is input C of the second decoder 49, the first input of the second group of input The decoder 41's output is its first output, the second-to-fifteenth output of which are respectively the outputs of the seventh to twentieth elements AND 50-63, the third input of the second group of inputs of the decoder 41 are the second inputs of the ninth to twelfth elements And 52-55, the first the inputs of which are connected to the corresponding outputs of the first decoder 48, the fourth input of the second group of inputs of the decoder 41 are the second inputs of the thirteenth to twentieth elements AND, the first inputs of which are connected to the corresponding outputs of the second decoder 49.

A shaper 42 comprises fifteen chains, each of which consists of an amplifier 64, the input of which is one of the inputs of the level generator, and the output of the amplifier 64 through the back diode 65 and the voltage divider 66 connected to the anode of the second diode 67, and the cathodes all fifteen second diodes 66 of each chain are connected through a resistor 68 to a common bus, and through a repeater 69 to the output of a driver 42 level.

The first inputs of the frequency comparator are the information inputs of the first register 70, the second group of inputs is the corresponding clock inputs of the first register 70, the outputs of which are connected to the corresponding information inputs of the second register 71 and the corresponding inputs of the second group of inputs of the second encoder 72, the inputs of the first group of inputs of which are connected to the corresponding outputs of the second register 71, the clock inputs of which are interconnected and are the fourth input of the comparators 32 and 33 frequencies, the third input of which is Interconnected clock inputs of the second trigger 73 "More and second trigger 74" Less, the reset inputs of which are interconnected and are the fifth input of the comparators 32 and 33 frequencies, and the outputs - the first and second outputs of the comparators 32, 33, respectively, while the information inputs of the second trigger 73 and 74 "More and" Less are connected respectively with the first and second outputs of the second encoder 72.

The device works as follows.

The change in the frequency deviation of the short signal from the nominal f, if the minimum / n-Afn and maximum fa-i-f deviations are known, is performed similarly to the analog-to-digital conversion method by bitwise weighting, i.e., determining the binary equivalent of the analog value, starting from the highest the binary bit, by comparing this value with half the maximum range, then determining the next bit of the binary equivalent, comparing the analog value with the quarter values of the maximum di apazona, etc.

Short signal of unknown frequency l; compared with frequency / and, if frequency, then "1, if, then" O, is recorded in the most significant bit of the binary equivalent, and the short realization of the input signal is stored on the delay line through which the stored input signal is circulated. If, then at the moment of pause in the circulation of the input signal occurs

frequency shaping equal to / + 4-A / ii,

2 and during the appearance of the input signal

the output of the delay line compares two frequencies if, -f-. then the second bit is equal to "1, if + - | -AfH, then the second bit is equal to" O.

Thus, the formation of a binary equivalent is carried out, the main difficulty in implementing such a method is the creation of a frequency comparator.

In the proposed device, a frequency comparator 32, 33 is applied, the electrical functional scheme of which is shown in FIG. 4, and the timing of the operation in FIG. 6 and 7. Signal 1 of comparator 32 (Fig. 4) receives a signal of unknown frequency fx (Fig. 6a, 7a), and a second group of inputs - a grid of phase-shifted reference frequency pulses / e, i.e., frequency tunable depending on the bit of the binary equivalent being defined, for example

taking values of f, / "- f- -A / K, / n-

--y-A / h, etc. If, more, faijc

i.e., the pulses of the reference frequency (Fig. 66, c, d) will shift to the right in Fig. 6 over time. 6 with respect to a pulse of unknown frequency (FIG. 6a).

After some time, the relative position of the pulses of the unknown and reference

frequencies will correspond to the image (Fig. 6a, b, e, d). Since the shifted pulses of the reference frequency arrive at the clock inputs of the D-flip-flops, which comprise the register 70 of the comparator 32 frequencies, and the pulses of unknown frequency go to the information input of these flip-flops, if they are located as shown in FIG. 6a, b, c, d, the state of the triggers of the first register 70, starting from the top, will be 1.10. This state of the pulse at input 4 is rewritten in the second register 71 as the previous state of the first register 70 for comparison with its subsequent state. At the point in time corresponding to FIG. ba, b, c, d, the state of the triggers of the first register 70 will be 100, and the second register 71 -110,

0, the second encoder 57 decrypts such a unit movement in the register code as and generates a potential at the input, which is impulse at input 3 stored on the second trigger 73 "More, and the subsequent impulse at input 4 will overwrite the state of the first register 70 in the second register 71 ( Fig. 7). In this case, the pulses of the reference frequency will move to the left with respect to the pulse of an unknown frequency (Fig. 7a). The second encoder 72 will decipher the change of the code 100-110, which will cause the appearance of the potential at the output "and the establishment in" 1 of the second trigger 74 "Less.

The main problem in the operation of this 32-point frequency controller is the provision of the necessary phase relationship between the reference and unknown frequencies. The ratio of the phases of the reference and unknown frequencies is understood to be the position of the leading edge of the reference frequency, during which

0 cycle implementation of an unknown frequency of this front edge in its movement due to the difference in frequency crossed any front of the signal of unknown frequency. FIG. 5, the frequency has the form of a horizontal straight line, since the phase difference of this frequency with the phase of frequency n, taken as zero, has a constant value and does not depend on time, for example, the AB section of FIG. 5. Along the Y axis, the phase difference is deposited in time units of the difference in the position of the research institute of the leading edges of the signals, therefore this difference cannot exceed the period Tn - this value limits the graph from above. The graph (Fig. 5) shows the segment max, which characterizes the frequency / n + A / n, and the segment min, which characterizes the frequency

5 f "-A / n. The VG segment (Fig. 5) characterizes the phase change of the unknown frequency fx entering the device input or as a result of recirculation on the delay line.

five

7

in this case, therefore, the straight VG has a negative slope.

As can be seen in the graph (Fig. 5), the AB and VG segments do not intersect, i.e. between the frequencies d: and / e there is no change in the phase difference, i.e. the leading edges of the pulses do not pass through each other, it means The operation condition of the comparator is not met. To eliminate this drawback in the device, by special selection of the frequency / e, several implementations of the AB, A | B |, A2B2, AzBz section (Fig. 5) were created. To clarify this fact, consider the joint work of two generators with periods T2 and TI.

For ease of understanding, it is assumed that the first generator with a period TI is the measured frequency / x, and the second generator is the frequency with a period Tc, the T2 is determined

T2 (1 + a) T ,, (I)

where a is the fractional part of the coefficient of proportionality.

It is assumed that the generators started working simultaneously, with each period of the second generator (T2) the phase difference increases by a, but this phase difference cannot be greater than the period Ti, then after a certain number q of periods T2, the condition

a ((7-1) 1 and a-q.

then in the -th period the leading edge of the second T2 generator will again come to the beginning of the TI period, but with some “deepening. P is the part of the period Ti, on which the leading edge of the second generator “will deepen beyond the leading edge of the first generator, as the first generator will have time to do (the period over the q periods of the second generator, then

, (9 + 1) + pT |. (3)

Taking into account equality (1) subject to (2) receive

.(four)

It follows that the th period of the second generator has a phase shift with respect to the phase of the first generator p, and the first period - “Oh, -f-1st period has a phase shift of a + p, and the second period - a, etc. ., i.e., each period of the second group of q periods of the second generator is shifted in phase with respect to the corresponding period of the first group of q periods by the value p.

Such a case for and (depicted in Fig. 5. Line DE - phase change of generator 1 for its first four periods, the leading edges of these periods are marked with letters A, AI, A2, AZ; lines D1E | - phase change of the reference generator for the second four periods , the leading edges are labeled A, A |, A2Az. Since the points A and A are on the horizontal straight line AB. Thus, four realizations of the frequency are obtained, corresponding to

22450о

about

by the slope of the direct frequency / n, and shifted with respect to each other by the magnitude of a Tn, namely, direct AB, A | B |, A2B2, AzBz. In addition, in order to improve the operation of the comparator, several implementations of the unknown frequency VG, V | G |, V2G2, VZGz, V4G4 are obtained, and its several branches of the delay line are diverted. Moreover, if the delay between the taps D Tn, and their number l, then comply 10A-Tn (n-1) 5 aTn- (5)

An even higher degree of fragmentation of the period Tn is obtained when, from the chosen implementation, / e is obtained using a delay line / (its implementations shifted among themselves by b-Tn, and

b-Tn () (6)

where b is the part of the period of the nominal frequency, which corresponds to the delay between the taps of the third delay line 41, i.e. ultimately, the period Tn is divided into q (n-1X-1) parts.

The command "Start is set to" 1 trigger 7 of the time interval and is held in this state until a single potential passes through the first element 8

 delay and will not reset the trigger 7 time interval in "O. At this time, the second element AND 9 opens, which passes the signal of unknown frequency i to the first 12 and second 13 delay lines. After reset

The OQ of the flip-flop 7 of the time interval in the "O" opens the third element AND 10, which closes the output of the first delay line 12 to its input, i.e., the measured signal is recirculated. The taps of the first delay line 12 are inputted to the information inputs of the analysis register 19, the output of the controlled oscillator 1 is entered at its synchronization input. The triggers of the analysis register 19 are recorded as "1, if / ,, taken from the first delay delay line 12, with its forward front ahead of front 40 research institutes front of the frequency of the generator 1, and “Oh, if it lags behind. The outputs of the analysis register 19 are assigned to the inputs of the modulo 20 summation module two, from which the signal "I, if the neighboring triggers of the analysis register 19 are removed

c are in different states.

Thus, the analysis register 19 analyzes the frequencies of the input 1 signal and the controlled oscillator 1 and finds the realization of the frequency / e between the realizations of the input signal taken from the branch of the first delay line 12, for example, the realization / e of A2B2 located between implementations / l B | G | and B2G2 (Fig. 5). The search and memorization of the realization of the frequency / s starts from the moment corresponding to the beginning of the recirculation of the measured signal /.j,

55 for which the first period of the measured signal from the output of the first delay line 12 is set to "L", the first control trigger 14, whose output signal is differentiated by the second driver 18 and sets to "1 second control trigger 15, which opens the fourth And 21 element at the third input , the second input of the fourth element And 21 is fed to the inverted frequency of the controlled oscillator 1, which ensures the operation of the fourth element And 21 with a delay of half the generator period.

The first input of the fourth element And 21 is connected to the last modulo 20.p circuit of modulo two, the inputs of which receive output signals from the first and last triggers of the analysis register 19. If these triggers are in opposite states, then the unit potential from the output of the last 20. modulo-sum circuit passes through the fourth And 21 element and gives permission to write to the delay selection register 24 the number of the selected tap of the first delay line 12 from the circuit summation, enables writing to the phase 4 register of the implementation number and resets the second control trigger 15, thereby prohibiting the fourth element 21 on the third input.

Counter 3 calculates (numbers) each period of the controlled oscillator 1, the phase of which moves from 0 to Tn and has as many states as the frequency realization adopted (in Fig. 5, the phase change corresponds to the direct DE, D1E1, D2E2, etc. .).

The signal from the fourth element And 21, corresponding to the choice of implementation, the state of counter 3 is rewritten into phase 4 register and enters comparison block 5, the other inputs of which receive values from counter 3. When the codes of counter 3 and phase register 4 coincide, the necessary implementation is selected frequency / e A2B2 between V | D | and B2G2 (Fig. 5). Selected implementation frequency /; through the first element, And 6 is fed to the third delay line 44, where a higher degree of fragmentation of the period Ti is reached, i.e., from the selected implementation, A2B2 is received on the third delay line 44 of its implementations K shifted among themselves by b-Tn (Fig. 5 ). The output signal from the delay selection register 24, corresponding to a pair of taps of the first delay line 12, is fed to the first input of one of the elements AND 29 of the switching unit 28, the second inputs receive the frequency fx from the taps of the first delay line 12. Thus, the switching unit 28 provides to the input of the comparators 32 and 33 frequencies the realization of the frequency / s of the selected taps of the first delay line 12 (Fig. 5 BiFi, B2G2). To the second inputs of the comparators 32 and 33 frequencies are supplied. To the realizations of the frequency f-i, taken from the taps of the third delay line 44. The third and fourth inputs of the comparators 32 and 33 frequencies receive signals from the third 45 and fourth 46 delay elements, which reset, respectively.

second register 71 and second trigger 74 “Less. The fifth input of the comparators 32 and 33 frequencies receives a signal from the second driver 18. During the measurement process there can be r several cases of comparing the input frequency / d; and fy.

The first case corresponds to the initial moment when the difference between fx and / e is significant. In this case, the second realization of the frequency / e A2B2 (Fig. 5) and the frequency of the input signal / BiFi and B2G2 (Fig. 5) are selected.

As can be seen from FIG. 5, the realization / h, corresponding to direct A2B2, does not intersect the realization of the input signal / V | T | and V2G9 from the moment of their choice, therefore, the frequency frequency dividers will not work. Thus, the nominal frequencies of the input fx taken from the selected taps of the first delay line 12 and В | Г | and B2G2 (Fig. 5), and the reference O selected according to the input time, are so far away that during the comparison time the frequency will shift / - and the analysis register 19 will trigger a new phase state of the signals corresponding to the following taps of the first delay line 12 whose analysis in modulo-two summing circuit 20 produces a result different from the delay selection register recorded in register 24 (implementation fx VCGS, FIG. 5), which goes to the first encoder 25, which analyzes the unit movement in the code of registers 24 and 19 and generates a signal tstvuet instances for A2B2.

After this potential, the duration of the signal of the controlled generator 1 will be written to the first trigger 26 "More and through the second element OR 34 will go to the fifth

5 element And 37 and the information entry of the register 40 result. On the fifth element 37, this potential is polled at the end of the recirculation by the signal from the first shaper 17, since the delay of the second delay element 16 is approximately equal to the recirculation cycle, the first trigger 14 of the control is reset to the new recirculation cycle. The signal from the output of the first element AND 37, passed through the fourth element OR 36, shifts by one bit

With a register of 39 cycles and writes "1 to the star-1PII bit of the register register 40 results. The outputs of the result register 40 and the cycle register 39 are sent to the decoder 41 to form the control potential, which, having passed through the level shaper 42, rebuilds the controlled oscillator 1 through the control element 2 to implement the next frequency. In the second cycle of operation, when in the result register 40 is “1, on the seventh element And 50 of the decoder 41 there occurs a coincidence of the potentials at the input,

5 the output potential of this element 3/4 through the shaper 42 and the control element 2 reconfigures the controlled oscillator 1 to the frequency realization

(corresponding to 3/4 of the range.

In the second cycle, the operation of the device is similar to that described, only the implementation / e is represented by the BZ, B1Zh1, BdZha, BZZhz (Fig. 5), and the implementation / in the process of recycling ZI, 3 | Hi, 32I2, ZZIz, 34I4 (Fig. 5) . In this case, the implementations will be chosen / e - B | W1 and / - ZI and 3iH |. The implementation / e crosses the lower implementation fx - ZI (FIG. 5), so the second frequency comparator 33 will work, which gives the potential, which means or means, in the second step, the result register 40 writes the “O and the binary equivalent code in two senior bits will be 10.

In the third cycle, the first decoder 48 of the decoder 41 will generate a potential at output 10, then the eleventh element And 54 will work and output a potential of 5/8, which switches the controlled oscillator 1 to fg f + -f-d fn corresponding to 5 / 8 range. In this case, the implementation of where F | Kj ZhgKa, ZhzKz, LCD. Selected will be the implementation of / e - ZhzKz and / - L2M2 and LzMz. Realizations of / e intersect the upper realization of fx - ЛзМз, then the first comparator of 32 frequencies will work, which gives a potential, i.e., or / e / dg, then in the third discharge of the result it will be written "1 and the three-digit result code will look like 101.

Further operation of the device continues the same until the last cycle, at which point the result register 40 is output to the device output through the block 43 of the elements. And the measurement ends there.

Claims (4)

1. A device for measuring the frequency deviation from the nominal value, containing a counter and first, second and third elements AND, distinguished by the fact that, in order to increase the range of convertible frequencies, the fourth, fifth and sixth elements AND, controlled by generator, control element, time interval trigger, first, second, third and fourth delay elements, phase register, comparison unit, first, second and third delay lines, first OR element, first and second control triggers, first and second drivers, p analysis gist, n modulo two summation circuits, first and second inverters, delay selection register, first encoder, first trigger "Greater, first trigger" A smaller switching unit containing n elements AND, second and third elements OR, first and second frequency comparators , fourth, fifth and sixth elements OR, cycle register, result register, decoder, level generator, block R of elements AND, start input, connected 5 .JQ 15 25 30 five five 0 five 0 with the reset input of the result register, the cycle register setup input and the time interval trigger setup input, the output of which is connected to the first input of the second I element, and the input of the first delay element whose output is connected to the reset input of the time interval trigger, the inverse output of which is connected to the first input The second element is And, the second input of which is connected to the output of the second delay line, and the output. - with the second input of the first OR element, the first input of which is connected to the output of the second element AND, the second input of which is the device input, the output of the first OR element is connected through the first delay line to the input of the second delay line and the installation input of the first control trigger, the output of which serially connected - the second delay element and the first driver are connected to the reset input of the first control trigger and the second inputs of the fifth and sixth elements AND, and through the second driver - with the fifth inputs the first and second frequency comparators, the reset inputs of the first trigger more and the first trigger less and the setup input of the second control trigger, the reset input of which is connected to the clock inputs of the phase register and the delay selection register, and the output of the fourth And element, the output of the second control trigger connected to the third input of the fourth element And, the second input of which is connected to the output of the first inverter, the input of which is connected to the clock inputs of the counter and analysis register, the second input of the first element And and the output of the controlled generator, the input of which is connected to the output of the control element, the input of which is connected to the output of the level generator, the inputs of which are connected to the corresponding outputs of the decoder, the inputs of the first group of inputs of which are connected respectively to the first inputs of the elements of the AND block and the corresponding outputs of the register , the inputs of the second group of inputs of the decoder are connected to the corresponding outputs of the cycle register, the output of which, corresponding to the highest bit, is connected to the second inputs And elements included in the block of elements I, and is one of the outputs of the device together with the outputs of elements AND of the block of elements And, n taps of the first delay line are connected to the corresponding information inputs of the analysis register and the second inputs of the corresponding elements And, included in the block switching, the first inputs of which are pairwise combined and connected to the corresponding inputs of the first group of inputs of the first encoder and the outputs of the delay selection register, whose information inputs are connected to the corresponding outputs Summing circuits modulo two n inputs of the second group of inputs of the first encoder, outputs “More and” Less than which are connected with information inputs of the first trigger “More and first trigger” Less, whose outputs are connected respectively with the third input of the fourth element and the second input of the fifth OR element, whose output connected to the first input of the sixth element And, the output of which is connected to the second input of the sixth element OR, the output of which is connected to the clock inputs of the register of cycles and the result register, the information input of which connected to the output of the fourth OR element and the first input of the fifth AND element, the output of which is connected to the first input of the sixth OR element, the counter outputs are connected respectively to the inputs of the second group of inputs of the comparison unit and the information inputs of the phase register, whose outputs are connected respectively to the inputs of the first group of inputs comparison unit, the output of which is connected to the first input of the first element I, the output of which through the second inverter is connected to the clock inputs of the first trigger "More and first trigger" Less than a directly - to the input of the third delay line, whose / C taps are connected to the inputs of the second input groups of the first and second frequency comparators, and the output via the third delay element to the third inputs of the first and second frequency comparators and through the third and fourth delay elements to the fourth inputs the first and second frequency comparators, the first inputs of which are connected respectively to the outputs of the second and third OR elements included in the switching unit, the outputs of the second OR element are connected respectively to the output Dami odd elements And input w, them in the switching unit, and the outputs of even elements - with the inputs of the third element OR, the first outputs of the first and second frequency comparators are connected respectively to the first and second inputs of the fourth element OR. and the second outputs are with the first and third inputs of the fifth OR element, the output of the lower bit of the analysis register is connected to the first input of the first of the modulo two summation circuits and the second input of the last n-circuit of the summation modulo two circuits, the output of which is connected to the first input of the fourth And element, the remaining outputs of the analysis register bits are connected as follows; the output of the second bit is connected to the second input of the first circuit from modulo two summation circuits and the first input of the second circuit from modulo two summation circuits, output one of the third bit - with the second input of the second and first input of the third circuit from modulo summation schemes, etc., the most significant bit of the analysis register is connected to the second input 0 0 five the last but one and the first input of the last modulo two sum scheme. 2. The device according to claim 1, characterized in that the decoder contains the element NOT, the first and second decoders, the seventh-twentieth elements AND, the first input of the first decoder group is the input of the element NO connected to the inputs A of the first and second decoders and the first input of the eighth element AND, the second input of which is the second inlet of the second group of inputs of the decoder and connected to the second input of the seventh element AND, the first input of which is connected to the output of the element NO, the second input of the first group of inputs of the decoder are interconnected inputs B p The first and second decoders and the third input is the input C of the second decoder, the first input of the second group of inputs of the decoder is its first output, and the second - the fifteenth outputs are respectively the outputs of the seventh to twentieth And elements, the third input of the second group of inputs of the decoder are the second the inputs of the ninety-twelfth And elements, the first inputs of which are connected to the corresponding outputs of the first decoder, the fourth input of the second group of inputs of the decoder are the second inputs of the thirteenth to twentieth elements And, the first inputs of which oedineny stvuyush.imi with corresponding outputs of the second decoder. 3. The device according to claim 1, characterized in that the level driver comprises fifteen amplifiers, fifteen first diodes, fifteen voltage dividers, fifteen second diodes, a resistor and a repeater, and fifteen chains are included in the level driver each of which consists of an amplifier, the input of which is one of the inputs of the level generator, the output of the amplifier through the back-connected first diode. The voltage divider is connected to the anode of the second diode, with the cathodes of all fifteen second diodes each second resistor chains are connected via a common bus and via a repeater - with the output of the level. 0 five 0 4. The device according to claim 1, wherein the frequency comparator contains the first and second registers, the second encoder, the second trigger "More and the second trigger" Less, the first input of the frequency comparator are interconnected information inputs of the first register, the second group of inputs - the corresponding clock inputs of the first register, the outputs of which are connected to the corresponding information inputs of the second register and the corresponding inputs of the second group the inputs of the second encoder, the inputs of the first group of inputs of which are connected to the corresponding outputs of the second register, the clock inputs of which are interconnected and are the fourth input of the frequency comparator, the third input of which are interconnected clock inputs of the second trigger "More and second trigger" Less, the reset inputs of which are interconnected and are the fifth input U / g.2 the frequency comparator, and the outputs, respectively, the first and second outputs of the frequency comparator, while the information inputs of the second trigger More and Less are connected respectively with the first and second outputs of the second encoder. FIG:} uj;