SU1319255A1 - Quasistatic counting device based on insulated-gate field-effect transistors - Google Patents

Abstract

The invention relates to a pulse technique. It can be used as a standard digital VLSI node. The purpose of the invention is to expand the functionality of the device. The device contains transistors 4-7, inverter 1, storage capacitor 8, push-pull amplifier 9. To achieve this goal, storage registers -12, 13, element OR 14, inverters 15-17, element 18, push-pull amplifiers 19, 20 are entered into the device , storage capacitors 21, 22, transistors 23-29. 2 Il. S (L with so to eat

Description

The invention relates to a pulse technique and can be used as a standard digital VLSI assembly. The purpose of the invention is to expand the functionality of the device by introducing an initial setting mode, a 1: 1, 2: 1 conversion mode, and an account management mode.

FIG. I shows a prince of an electric circuit of a quasistatic counting device on MIS transistors; in fig. 2 - time diagrams of his work.

The device contains the first inverter 1 connected between the power supply bus 2 and the common bus 3, the pass-through transistor 4, three controllers, their transistors 5-7, the first storage capacitor 8 and the first push-pull amplifier 9 consisting of series-connected repeater and an inverting transistor, where the source of the inverting transistor of the two-phase amplifier is connected to the common bus 3, the output of the first inverter 1 through the second control transistor 6 is connected to the inverting input of the first push-pull amplifier 9, the output of the first two The active amplifier is connected to the first plate of the first storage capacitor 8, to the drain of the third control transistor 7 and to the transfer pulse bus 10, the gate of the repeater transistor of the first push-pull amplifier 9 is connected to the second plate of the first storage capacitor 8 and to the drain of the first control transistor 5, the drain of the pass-through transistor 4 is connected to the output of the first inverter 1, the gates of the pass-through 4 of the first 5 and the second 6 of the control transistors are connected to a clock 11 clock signals, the bit of the memory re-. conversion source 12, preset storage register 13, element OR 14, second 15, third 16 and fourth 17 inverters, And 18 element, second 19 and third 20 push-pull amplifiers, second 21 and third 22 storage capacitors, first 23 and the second is 24 cut-off transistors, the first is 25, the second is 26, the third is 27, the fourth is 28, and the Fifth is 29 switching transistors. Moreover, the bits of the storage registers of recalculation 12 and preset 13, element OR 14, element 18, second 15, third 16 and fourth 17 inverters 15 are connected between power supply 2 and total thickness 3. The output of element 18 is connected to the input of the first the inverter 1 and the source of the first control transistor 5. The first input of the element I 18 is connected to the sources of the pass 4 and the third 7 of the control transistor The input of the second inverter 15 through the first switching transistor 25 is connected to the account control bus 30, and its output is to the first input of the element OR 14 and shutter inverting transistor second

push-pull amplifier 19. The second input element OR 14 through the second switching transistor 26 is connected to the input bus 31. installation, the output of the element OR 14 through the first cut-off transistor 23 is connected to the gate of the repeater transistor of the second push-pull amplifier 19 and the first plate of the second storage capacitor 21. The output of the second push-pull amplifier 19 is connected to the second plate of the second storage capacitor 21, the drain of the repeating transistor of the first two-stroke amplifier 9 and the gate of the third control transistor 7. The drain of the repeater transistor of the second push-pull amplifier 19 is connected to the bus 32 of the counting pulses. The inputs of the bits of the memory register 12 conversion and storage register 13 preset through the third 27 and fourth 28 switching transistors are connected to the control bus conversion and preset 33, and their outputs, respectively, to the second input element And 18 and the drain of the transistor 34 preset. The input of the third inverter 16 through the fifth switching transistor 29 is connected to the initial installation bus 31, and its output is connected to the input of the fourth inverter 17 and the inverting input of the third push-pull amplifier 20. The output of the fourth inverter 17 is connected to the repeat input of the third push pull the amplifier 20 and the first plate of the third storage capacitor 22, the second plate of which is connected to the output of the third push-pull amplifier 20 and the gate of the transistor 34 preset. The source of the transistor 34 of the preset is connected to the first input of the I 18 element. The gates of the first 25, second 26 and the second 29 switching transistors are connected to the clock bus 11, and the gates of the cut-off transistors 23 and 24 are connected to the power supply 2. The drain of the repeating transistor of the third push-pull amplifier 20 is connected to the bus 32 counting pulses. The gate of the third switching transistor 27 is connected to the counting record writing bus 35, and the fourth switching transistor 28 gate is connected to the preset recording bus 36.

FIG. 2 shows the time diagrams in the main nodes (see 11, 30-33, 35-45) of the device during its operation in all functional modes. During to-tg, the device operation is shown when the device is preset to “O and“ 1. At the time of to-tg and t22-126 is the mode of prohibition of the account, tg-122 is the mode of resolution of the account. At the time of tg-ti6 - recalculation 2: 1, and at the time - recalculation 1: 1.

Consider the operation of the functional units of the device in the mode of presetting the counting trigger in “O (to-t time)

and in “1 (time t4-tg). At the considered time, the device is switched to the mode of prohibition of the account for the purpose of greater operational efficiency (although presets can occur in the mode of account). The preset is not implemented in 1: 1 counting mode. To implement the preset, the device receives the following signals. The bar 33 receives a low voltage level to ensure that the device switches to the 2: 1 recalculation mode. With the arrival of a pulse on the counting mode write 35 (time ti-12) at the input of the element 18, a high potential is established, as a result of which the counting trigger goes into the 2: 1 counting mode. The bus 30 receives a low voltage level, and with the arrival of a clock pulse (time to-1 |), a high potential is established at the input of the OR 14 element, and a low potential at the input of the amplifier 19, resulting in no counting pulses from 32 counting pulses to the output of the amplifier 19, to the gate of the transistor 7, and to the drain of the repeater transistor of the amplifier 9. As a result, the counting flip-flop is set to any one state "O or" 1. Suppose that it is set to the "O" state and the output of the element 18 is set to a high level, the output of the inverter 1 and the input level of the element 18 through the transistor 4 is set to a low level. Low potential is supplied to the pin 33 to provide a preset of the counting trigger in the "A. By the preset recording impulse arriving at the bus 36 (time t, -t), the low potential from box 33 is overwritten and stored at the register bit 13. A high potential is established at its output. To implement the preset, a pulse (time ti-ta) must be applied to the preset bus 31. During a clock pulse (t2- |: h), the signal from band 31 is rewritten to the input of inverter 16, as a result of which a high signal level is established at the repetitive input of amplifier 20 and a low level at its inverse. At its output (since the counting pulses are low on the cheek), a low level is also set. When a 32 pulse arrives at the terminal, it is transmitted through an open repeating transistor to the output of amplifier 20 and to the gate of the transistor. Increasing the output potential through the storage capacitor 22 is transmitted to the input of the amplifier 20, and at the latter a potential higher than the supply voltage level is set. In order to avoid the discharge of the capacitor 22 to the power supply bus, a transistor 24 is used, which at this time is closed at the source. Due to the fact that at the input of the amplifier 20, the potential during the formation of pulse 0

five

0

five

0

five

0

five

0

five

At its output, it exceeds the potential of the power feed, at the indicated output, the pulse amplitude is equal to the pulse amplitude on the counting chip.

With the arrival of a pulse at the gate of transistor 34, a high level is transmitted to the first input of the element And 18, as a result of which a low level is established at its output and a high level at the output of inverter 1. During the installation of the potential, transistors 4 and 7 are closed by low levels at their gates (time ti- (4), which ensures high reliability and speed of the preset due to the high impedance state of the input element And 18). Transistor 7 is closed by a low potential at the output amplifier 19. In counting mode, the counting pulse is blocked by the second input of the element OR 14 during the preset pulse action on the busbar 31. In the same way, the preset is set to "1 (time t4-tg). The only distinctive feature is that and AND 18 is overwritten with the low level output register 13. At the time tn-tg schine 30 on low voltage level blocks the passage of countable pulses to the output amplifier 19, so that on schine 10 is set low, i.e. no transfer pulses.

At time t (o-tji on the bus 30 there is a high potential - this is the counting mode. Moreover, during the tio-tie, the count mode is 2: 1, i.e. every second counting pulse is formed on the bus 10. With a high level coming to the bus 30 during a clock pulse (tio-tii), this level is transmitted to the input of the inverter 15, as a result of which the pa inverting input of the amplifier 19 is set to a high level, and at the repeating input of the amplifier 19 - low, which allows the passage of counting pulses to the output of the amplifier 19. Capacitor 21 and transistor 7 provide in formation time and pulses at the output of amplifier 19 increase the potential at the repeating input of amplifier 19, exceeding its level of supply voltage. As a consequence, the amplitude of the pulses at the output of amplifier 19 is equal to the amplitude of the counting pulses. And the pulses at its output form until the input potential is high.

The operation of the device in the 2: 1 counting mode (tio-122) is as follows. Since the output of the element 18 is high and the voltage on the output of inverter 1 is low, during the clock pulse (ts-tg), the inputs of the amplifier 9 are set to high and low levels respectively. With the arrival of PA output amplifier 19 counting pulse

(tg-t

MO HE is transmitted through open

the repeater transistor amplifier 9 to the bus 10 and through the transistor 7 to the input element And 18. With a high potential at its input a low level is set at the output of the element 18, and high at the output of the inverter 1. Bus 10 generates a pulse amplitude equal to the amplitude of the counting pulses on bus 32 due to capacitor 8. At the end of the counting pulse at the output of amplifier 19, transistor 7 closes, but a high level is stored at the input capacitance of the element input 18. With the arrival of a clock pulse, a high level at this the input is supported by the transistor 4, which at the time of the clock pulses is connected to the output of the inverter 1 ia the first input of the element 18. During the operation of the clock pulse (ti2-iis) at the inputs of the amplifier 9 avlivayuts through transistors 5 and 6, respectively, low and high levels. With the arrival of the next counting pulse {li.j-tu) at the output of amplifier 19, it does not pass through the closed Tbn i repeater transistor of amplifier 9 to 10, and the last remains low. Through the transistor 7, a low potential is established at the first input of the element 18, therefore, the outputs of the element 18 and the inverter 1 are set to high and low levels respectively. The clock pulse (i 4-tis) through the transistors 5 and 6 at the inputs of the amplifier 9 are set respectively high and low levels. With the arrival of the next counting pulse (ti5-ti (i), a pulse is formed on bus 10, and a high level is established at the first input of the element And 18, i.e. the state (ti 1-ti2) repeats. Thus, in this mode every second counting impulse passes to the bus I), i.e., a 2: 1 recalculation takes place.

During ti6-i 7, the counting mode write pulse on bus 35, at the output of the bit of storage register 12, is set to low potential in accordance with. the potential on the bus 33. As a result, the outputs of the element And 18 and inverter 1 are set and maintained respectively high and low levels (time t, b-tis). The clock pulse {time t | fe -t, d) a high level from the output of the element And 18 through the transistor 5 is transmitted to the repeater input of the amplifier 9, and a low level from the output of the inverter 1 through the transistor 6 is transmitted to the inverting input of the amplifier 9. With the arrival At the output of the amplifier 19 of the next counting pulse (ti7-tis time), a pulse is formed on the bus 10. Since during subsequent clock pulses the levels at the inputs of amplifier 9 remain

high and low, respectively, then pulses are formed on bus 10 with the amplifier 19 of each counting pulse arriving at the output, i.e. 1: 1 recalculation takes place. With the arrival on the bus 30 low (tai-126) on the clock pulse (t22-12.3)

at the input of the element OR 14, a high level is established and blocks the passage of counting pulses to the output of amplifier 19, i.e., it switches the device to the counting prohibition mode. Thus, the quasistatic counting device on MOS transistors provides control of the account (prohibition of the account and resolution of the account), two modes of the account (recalculation 2: 1 and recalculation 1: 1), the initial setting counts 1

trigger in “Oh and in“ 1.

five

Claims (1)

Invention Formula Quasistatic counting device on 0 MDP transistors containing the first inverter connected between the power bus and the common bus, a pass-through transistor, three control transistors, the first storage capacitor and the first push-pull amplifier consisting of sequentially connected repeating and inverting transistors, and the source of the inverting transistor of the push-pull amplifier connected to the common bus; the output of the first inverter through the second control; the transistor is connected to the inverting input of the first push-pull amplifier; the output of the first two-step Nogo amplifier connected to a first electrode of the first storage capacitor to the drain I peTbei of the control transistor and to the bus 5 transfer pulses, the gate of the repeating transistor of the first push-pull amplifier are connected to the second plate of the first storage capacitor and to the drain of the first control transistor, the drain of the pass-through transistor is connected to the output of the first inverter, the gates of the first and second control transistors are connected to the clock switch skgnalo.z. characterized by the fact that, in order to expand the functional capabilities of the device, it additionally introduces a digit of the conversion register, the storage register preset memory, the OR element, the second, third and fourth inverters, the AND element, the second and third storage capacitors, the second and third two-way clock amplifiers, the first and second cut-off transistors, the preset transistor, the first, second, third, fourth and fifth switching transistors, the register preset register, the start bit Mina translation register, 5 OR element, AND element, the second, third and fourth inverters are connected between the power bus and the common bus; AND output element is connected to the input of the first the inverter and the source of the first control transistor, the first input of the element I is connected to the sources of the pass-through and the third control transistor, the input of the second inverter through the first switching transistor is connected to the account control bus, and its output is connected to the first input of the OR element and the inverting input of the second push-pull amplifier, the second input element OR through the second switching transistor is connected to the bus of the initial installation, the output of the element OR through the first cut-off transistor is connected to the repeater the second push-pull amplifier and to the first plate of the second storage capacitor, the output of the second push-pull amplifier is connected to the second plate of the second storage capacitor, to the drain of the repeater transistor of the first push-pull amplifier and to the gate of the third control transistor, the second push-pull amplifier is connected to the busbar counting pulses, the inputs of the bits of the memory register conversion and memory register reset through the third and fourth switching transistors connected to the control and pre schine recalculation, and their outputs respectively; to the second input of the Ink element of the preset transistor, the input of the third inverter through the fifth switching transistor is connected to the initial setup bus, and its output to the input of the fourth inverter and the inverting input of the third push pull amplifier, the fourth inverter output through the second shedding transistor connected to the repeater input of the third push-pull amplifier and to the first plate of the third storage capacitor, the second cover of the third storage capacitor is connected to the output of the third uhtaktnogo amplifier and to the gate of the preset transistor, whose source is connected to the first input of the AND gate, the first gates. the second and fifth switching transistors are connected to the clock signal bus, the drain of the repeating transistor of the third push-pull amplifier is connected to the counting pulse bus, the gate of the third switching transistor is connected to the counting record recording bus, and the plug of the fifth switching transistor is connected to the preset recording bus. 0 35 -t..Y Yi i Vf Y M: l 1 .G. I i g I I i 1 il I I 35 37 36 3) 32 ze ..(one sh / shshshgad 5 "fc7H33 ± eih ± HEl" I 41 so hell "" liliiMn n ITTT I I I I I I H I M -US dftm five -US PLIMA Compiled by A. Kabanov Editor O. BugirTehred And WeresKorrektor M. Demchik Order 2530/55 Circulation 901 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk emb. 4/5 Production and printing company, Uzhgorod, ul. Project, 4